메뉴 건너뛰기




Volumn 43, Issue 7, 2008, Pages 71-78

Improving performance and reducing energy-delay with adaptive resource resizing for out-of-order embedded processors

Author keywords

Architecture; Energy Delay; Out of Order Embedded Processor; Performance; Resource Resizing

Indexed keywords

ARCHITECTURE; BUDGET CONTROL; CLOCKS;

EID: 67650093493     PISSN: 15232867     EISSN: None     Source Type: Journal    
DOI: 10.1145/1379023.1375668     Document Type: Article
Times cited : (1)

References (22)
  • 1
    • 27944468674 scopus 로고    scopus 로고
    • A. Terechko, M. Garg, H. Corporaal, Evaluation of speed and area of clustered VLIW processors, VLSI Design, 2005. 18th International Conference on, no., pp. 557-563, 3-7 Jan. 2005.
    • A. Terechko, M. Garg, H. Corporaal, "Evaluation of speed and area of clustered VLIW processors," VLSI Design, 2005. 18th International Conference on, vol., no., pp. 557-563, 3-7 Jan. 2005.
  • 3
    • 0038008204 scopus 로고    scopus 로고
    • Banked Multiported Register Files for High-Frequency Superscalar Microprocessors
    • San Diego, California, USA, 9-11 June
    • J.H. Tseng, K. Asanovic, et al., "Banked Multiported Register Files for High-Frequency Superscalar Microprocessors", International Symposium on Computer Architecture, San Diego, California, USA, 9-11 June 2003.
    • (2003) International Symposium on Computer Architecture
    • Tseng, J.H.1    Asanovic, K.2
  • 6
    • 17644379115 scopus 로고    scopus 로고
    • Increasing Processor Performance through Early Register Release
    • O. Ergin, et al., "Increasing Processor Performance through Early Register Release", Int'l Conference on Computer Design, 2004.
    • (2004) Int'l Conference on Computer Design
    • Ergin, O.1
  • 8
    • 0031374601 scopus 로고    scopus 로고
    • Keith I. Farkas, Paul Chow, Norman P. Jouppi, and Zvonko G. Vranesic. The Multicluster architecture: Reducing cycle time through partitioning. In MICRO-30, pages 149-159, 1997.
    • Keith I. Farkas, Paul Chow, Norman P. Jouppi, and Zvonko G. Vranesic. "The Multicluster architecture: Reducing cycle time through partitioning." In MICRO-30, pages 149-159, 1997.
  • 9
    • 84948974859 scopus 로고    scopus 로고
    • A. Seznec, E. Toullec, and O. Rochecouste. Register write specialization register read specialization: A path to complexity-effective wide-issue superscalar processors. In MICRO-35, Turkey, November 2002.
    • A. Seznec, E. Toullec, and O. Rochecouste. "Register write specialization register read specialization: A path to complexity-effective wide-issue superscalar processors." In MICRO-35, Turkey, November 2002.
  • 10
    • 67650045587 scopus 로고    scopus 로고
    • R. Balasubramonian, S. Dwarkadas, and D.H. Albonesi. Reducing the complexity of the register file in dynamic superscalar processors. In MICRO-34, December 2001.
    • R. Balasubramonian, S. Dwarkadas, and D.H. Albonesi. "Reducing the complexity of the register file in dynamic superscalar processors." In MICRO-34, December 2001.
  • 11
    • 67650074441 scopus 로고    scopus 로고
    • IBM Corporation. PowerPC 750 RISC Microprocessor Technical Summary. www.ibm.com.
    • IBM Corporation. PowerPC 750 RISC Microprocessor Technical Summary. www.ibm.com.
  • 16
    • 33947129173 scopus 로고    scopus 로고
    • Dynamic Resizing of Superscalar Datapath Components for Energy Efficiency
    • February
    • D. Ponomarev, G. Kucuk, K. Ghose, "Dynamic Resizing of Superscalar Datapath Components for Energy Efficiency," IEEE Transactions on Computers, vol. 55, no. 2, pp. 199-213, February, 2006.
    • (2006) IEEE Transactions on Computers , vol.55 , Issue.2 , pp. 199-213
    • Ponomarev, D.1    Kucuk, G.2    Ghose, K.3
  • 19
    • 84869371576 scopus 로고    scopus 로고
    • "Cacti4," http://quid.hpl.hp.com:9081/cacti/.
    • Cacti4
  • 22
    • 0036116742 scopus 로고    scopus 로고
    • A low-power RISC microprocessor using dual PLLs in a 0.13/spl mu/m SOI technology with copper interconnect and low-k BEOL dielectric
    • S. Geissler et al., "A low-power RISC microprocessor using dual PLLs in a 0.13/spl mu/m SOI technology with copper interconnect and low-k BEOL dielectric", in ISSCC 2002.
    • ISSCC 2002
    • Geissler, S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.