rePLay: A hardware framework for dynamic optimization

IEEE Transactions on Computers

Volumn 50, Issue 6, 2001, Pages 590-608

  Patel, Sanjay J ^a,b   Lumetta, Steven S ^a,b  

^a IEEE   (United States)

^b University of Illinois at Urbana Champaign   (United States)

Author keywords

Dynamic optimization; High performance microarchitecture; Trace caches

Indexed keywords

TRACE CACHES;

ALGORITHMS; CACHE MEMORY; CODES (SYMBOLS); COMPUTER ARCHITECTURE; COMPUTER HARDWARE; OPTIMIZATION;

PROGRAM PROCESSORS;

EID: 0035363244     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.931895     Document Type: Article

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