Two-bit cell operation in diode-switch phase change memory cells with 90nm technology

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2008, Pages 98-99

  Kang, D H ^a   Lee, J H ^a   Kong, J H ^a   Ha, D ^a   Yu, J ^a   Um, C Y ^a   Park, J H ^a   Yeung, F ^a   Kim, J H ^a   Park, W I ^a   Jeon, Y J ^a   Lee, M K ^a   Song, Y J ^a   Oh, J H ^a   Jeong, G T ^a   Jeong, H S ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; CELLS; CYTOLOGY; NANOTECHNOLOGY; RANDOM ACCESS STORAGE; SEMICONDUCTOR STORAGE; TECHNOLOGY;

90 NM TECHNOLOGY; BIT CELL; CELL OPERATIONS; INTERMEDIATE RESISTANCE; KEY FACTORS; PHASE CHANGE MEMORY CELLS; PHASE-CHANGE RANDOM ACCESS MEMORY; RESISTANCE INCREASE; RESISTANCE STATES; VLSI TECHNOLOGIES; WRITE DISTURBANCE;

PHASE CHANGE MEMORY;

EID: 51949114502     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2008.4588577     Document Type: Conference Paper

References (3)

1. J. H. Oh et al., IEDM Tech. Dig., pp.2.6.1-2.6.4 (2006).
2. K.-J. Lee et al. ISSCC Dig. of Tech. Papers, p. 472 (2007).
3. A. Pirovano et al., IEEE Trans. on Elect. Dev., 51(5), 714 (2004).