1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory cell efficiency of 33%

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2000, Pages 279-282

  Yokoyama, Yuji ^a   Itoh, Nobutaka ^a   Katayama, Masahiro ^a   Takashima, Kazumasa ^a   Akasaki, Hiroshi ^a   Kaneda, Masayuki ^a   Ueda, Toshitsugu ^a   Tanaka, Yousuke ^a   Yamsaki, Eiji ^a   Todokoro, Masaya ^a   Toriyama, Keinosuke ^a   Miki, Hiroshi ^a   Yagyu, Masayoshi ^a   Kobayashi, Toru ^a   Miyaoka, Syuichi ^a   et al , ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; DECODING; DYNAMIC RANDOM ACCESS STORAGE; ELECTRIC CURRENTS; ELECTRIC POWER SUPPLIES TO APPARATUS; INTERFACES (COMPUTER); LOGIC GATES; SPURIOUS SIGNAL NOISE;

DATA TRANSLATION RATE; MEMORY CELL EFFICIENCY; MULTIWORD REDUNDANCY SCHEME; ROW ADDRESS STORAGE ACCESS; SINGLE SIDE INTERFACE ARCHITECTURE;

INTEGRATED CIRCUIT LAYOUT;

EID: 0033698759     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)