A low power phase-change random access memory using a data-comparison write scheme

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2007, Pages 3014-3017

  Yang, Byung Do ^a   Lee, Jae Eun ^a   Kim, Jang Su ^a   Cho, Junghyun ^a   Lee, Seung Yun ^b   Yu, Byoung Gon ^b  

^a Chungbuk National University   (South Korea)

^b Electronics and Telecommunications Research Institute (ETRI)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DATA REDUCTION; ELECTRIC POWER UTILIZATION; PHASE CHANGE MEMORY; POWER ELECTRONICS;

DATA STORAGE; DATA-COMPARISON USE; DATA-COMPARISON WRITE (DCW); RANDOM ACCESS MEMORY;

RANDOM ACCESS STORAGE;

EID: 34548825142     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iscas.2007.377981     Document Type: Conference Paper

References (3)

1. Hyung-rok Oh, et al., "Enhanced Write Performance of a 64-Mb Phase-Change Random Access Memory," IEEE J. Solid-State Circuits, Vol. 42, No. 1, pp. 122-126, Jan. 2006.
2. Woo Yeong Cho, et al., "A 0.18-μm 3.0-V 64-Mb Nonvolatile Phase-Transition Rrandom Access Memory (PRAM)," IEEE J. Solid-State Circuits, Vol. 40, No. 1, pp. 293-300, Jan. 2005.
3. Y. N. Hwang, et al, "Full integration and reliability evaluation of phase-change RAM based on 0.24μm-CMOS technologies," in Symp. VLSI Technology Dig., 2003, pp. 173-174.