Interconnect modeling for improved system-level design optimization

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2008, Pages 258-264

  Carloni, Luca ^a   Kahng, Andrew B ^b   Muddu, Swamy ^b   Pinto, Alessandro ^c   Samadi, Kambiz ^b   Sharma, Puneet ^b  

^a Columbia University ^*  (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACCURATE MODELING; DEEP-SUB MICRON; DESIGN AUTOMATION CONFERENCE; DESIGN PHASE; FUTURE TECHNOLOGIES; IMPROVED SYSTEM; INTERCONNECT CIRCUITS; INTERCONNECT MODELING; LAYOUT DESIGNS; NETWORK-ON-CHIP; OPEN SOURCES; POWER-EFFICIENT; SOUTH PACIFIC; SYNTHESIS TOOLS; SYSTEM DESIGNS; SYSTEM LEVELS; SYSTEM-LEVEL OPTIMIZATION;

COMPUTER AIDED DESIGN; DIGITAL INTEGRATED CIRCUITS; ELECTRIC NETWORK TOPOLOGY; INDUSTRIAL ENGINEERING; NETWORKS (CIRCUITS); TECHNOLOGY; TURBULENT FLOW;

OPTIMIZATION;

EID: 49549112219     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2008.4483952     Document Type: Conference Paper

References (29)

1. S. N. Adya and I. L. Markov, "Fixed-Outline Floorplanning: Enabling Hierarchical Design", IEEE Trans. VLSI Systems, 11(2), 2003, pp. 1120-1135.
2. R. Arunachalam, F. Dartu and L. Pileggi, "CMOS Gate Delay Models for General RLC Loading", Proc. ICCD, 1997, pp. 224-229.
3. H. Bakoglu, Circuits, Interconnections and Packaging for VLSI, Addison-Wesley, 1990.
4. L. Benini and G. D. Micheli, "A New SoC Paradigm", IEEE Computer, 35(1), 2002, pp. 70-78.
5. Y. Cao, C. M. Hu, X. J. Huang, A. B. Kahng, S. Muddu, D. Stroobandt and D. Sylvester, "Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Design", Proc. IEEE ICCAD, 2000, pp. 56-61.
6. L. P. Carloni, R. Passerone, A. Pinto and A. L. Sangiovanni-Vincentelli, "Languages and Tools for Hybrid Systems Design", Foundations and Trends in Electronic Design Automation, 1, 2006, pp. 1-194.
7. J. Cong and D. Z. Pan, "Interconnect Delay Estimation Models for Synthesis and Design Planning", Proc. IEEE ASPDAC, 1999, pp. 507-510.
8. W. J. Dally and B. Towles, "Route Packets, Not Wires: On-Chip Interconnection Networks", Proc. ACM/IEEE DAC, 2001, pp. 684-689.
9. F. Dartu, N. Menezes and L. Pileggi, "Performance Computation for Precharacterized CMOS Gate with RC Load", IEEE Trans. on CAD, 1996, pp. 544-553.
10. S. Heo and K. Asanovic, "Replacing Global Wires With an On-Chip Network: A Power Analysis", Proc. ISLPED, 2005, pp. 369-374.
11. K. W. Mai, R. Ho and M. A. Horowitz, "The Future of Wires", Proc. IEEE, 2001, pp. 490-504.
12. International Technology Roadmap for Semiconductors, http://www.itrs.net .
13. LEF/DEF Exchange Format, http://openeda.si2.org/projects/lefdef .
14. Liberty File Format, http://www.synopsys.com/products/libertyccs/ libertyccs.html .
15. G. D. Micheli and L. Benini, Networks on Chip, Morgan Kaufmann, 2006.
16. D. Pamunuwa, L.-R. Zheng and H. Tenhunen, "Maximizing Throughput over Parallel Wire Structures in the Deep Submicrometer Regime", IEEE Trans. on VLSI Systems 11, 2003, pp. 224-243.
17. L. Pillage and R. Rohrer, "Asymptotic Waveform Evaluation for Timing Analysis", IEEE Trans. on CAD 9, 1990, pp. 352-366.
18. A. Pinto, A. Bonivento, A. Sangiovanni-Vincentelli, R. Passerone and M. Sgroi, "System Level Design Paradigms: Platform-Based Design and Communication Synthesis", ACM TODAES, 11(3), 2006, pp. 537-563.
19. A. Pinto, L. P. Carloni and A. L. Sangiovanni-Vincentelli, "A Methodology and an Open Software Infrastructure for Constraint-Driven Synthesis of On-Chip Communications", Technical Report UCB/EECS-2007-130, Nov. 2007.
20. Predictive Technology Model, http://www.eas.asu.edu/U∼ptm/
21. A. Raghunathan, N. K. Niraj and S. Dey, High-Level Power Analysis and Optimization, Kluwer, 1998.
22. C. Ratzlaff and L. Pillage, "RICE: Rapid Interconnect Circuit Evaluation using AWE ", IEEE Trans. on CAD 13, 1994, pp. 763-776.
23. S. M. Rossnagel and T. S. Kuan, "Alteration of Cu Conductivity in The Size Effect Regime", J. Vacuum Science Tech. B 22, 2004, pp. 240-247.
24. P. Saxena, N. Menezes, P. Cocchini and D. A. Kirkpatrick, "Repeater Scaling and its Impact on CAD", IEEE Trans. on CAD 23, 2004, pp. 451-462.
25. M. Shao, M. Wong, H. Cao, Y. Gao, L.-P. Yuan, L.-D. Huang and S. Lee, "Explicit Gate Delay Model for Timing Evaluation", Proc. ACM/IEEE ISPD, 2003, pp. 32-38.
26. S. X. Shi and D. Z. Pan, "Wire Sizing and Shaping with Scattering Effect for Nanoscale Interconnection", Proc. IEEE ASPDAC, 2006, pp. 503-508.
27. V. Soteriou, N. Eisley, H. Wang and L.-S. Peh, "Polaris: A System-Level Roadmap for On-Chip Interconnection Networks", Proc. ICCD, 2006, pp. 134-142.
28. D. Sylvester and K. Keutzer, "A Global Wiring Paradigm for Deep Submicron Design", IEEE Trans. on CAD 19, 2000, pp. 242-252.
29. http://vlsicad.ucsd.edu/GSRC/ .