SCOPUS 정보 검색 플랫폼

Volumn , Issue , 2006, Pages 301-306

A system-level network-on-chip simulation framework with analytical interconnecting wire models

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN STAGES; INTERCONNECTING WIRES; POWER ANALYSIS;

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; MATHEMATICAL MODELS; POWER CONTROL; ROUTERS; TELECOMMUNICATION LINKS;

MICROPROCESSOR CHIPS;

EID: 34250831419 PISSN: None EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/EIT.2006.252176 Document Type: Conference Paper

Times cited : (5)

References (13)

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2
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3
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4
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- Transaction Level Modeling: An Overview
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- Cai, L.¹ Gajski, D.²

5
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- VHDL-based Simulation Environment for PROTEO
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- (2002) Proc. of HLDVT Workshop
- Tortosa, D.S.¹

6
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- NoCGen: A Template-Based Reuse Methodology for NoC Architecture
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- Chen, J.¹

7
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- ORION: A Power-Performance Simulator for Interconnection Networks
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8
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- NoC Simulations for Benchmarking
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9
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- A High-level Interconnect Power Model for Design Space Exploration
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10
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- Addision-Wesley
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12
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13
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- Berkeley Predictive Technology Model and BSIM4

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.