Architectures and synthesis algorithms for powerefficient bus interfaces

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 19, Issue 9, 2000, Pages 969980-

  Benini, Luca ^a   Macii, Alberto ^a   Macii, Enrico ^b   Poncino, Massimo ^b   Scarsi, Ricardo ^b  

^a UNIVERSITY OF BOLOGNA   (Italy)

^b POLITECNICO DI TORINO   (Italy)

Author keywords

Bus encoding; Digital systems; Lowpower design

Indexed keywords

EID: 33747466024     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (10)

1. M.R. Stan and W. P. Burleson, "Businvert coding for lowpower I/O," IEEE Trans. VLSI Syst.. vol. 3, pp. 4958, Mar. 1995.
2. L. Benini, G. De Micheli, E. Macii, D. Sciuto, and C. Silvano, "Asymptotic zerotransition activity encoding for address busses in lowpower microprocessorbased systems," in Proc. GLSVLSI97: IEEE/ACM 7th Great Lakes Symp. VLSI, UrbanaChampaign, IL, Mar. 1997, pp. 7782.
3. E. Musoll, T. Lang, and J. Cortadella, "Workingzone encoding for reducing the energy in microprocessor address buses," IEEE Trans. VLSI Syst.. vol. 6, pp. 568572, Dec. 1998.
4. M.R. Stan and W. P. Burleson, "Lowpower encodings for global communication in CMOS VLSI," IEEE Trans. VLSI Syst., vol. 5, pp. 444455, Dec. 1997.
5. H. Mehta, R.M. Owens, and M. J. Irwin, "Some issues in gray code addressing," in Proc GLSVLSI96: IEEE/ACM 6th Great Lakes Symp. VLSI, Ames, IA, Mar. 1996, pp. 178180.
6. L. Benini, G. De Micheli, E. Macii, M. Poncino, and S. Quer, "Reducing power consumption of corebased systems by address bus encoding," IEEE Trans. VLSI Syst., vol. 6, pp. 554562, Dec. 1998.
7. S. Ramprasad, N.R. Shanbhag, and I. N. Hajj, "Informationtheoretic bounds on average signal transition activity," IEEE Trans. VLSI Syst., vol. 7, pp. 359368, Sept. 1999.
8. "A coding framework for low power address and data busses," IEEE Trans. VLSI Syst., vol. 7, pp. 212221, June 1999.
9. "Signal coding for low power: Fundamental limits and practical realizations," IEEE Trans. Circuits Syst. II, vol. 46, pp. 923929, July 1999.
10. L. Benini, G. De Micheli, E. Macii, D. Sciuto, and C. Silvano, "Address bus encoding techniques for systemlevel power optimization," in Proc. DATE98: IEEE Design Automation and Test in Europe, Paris, France, Feb. 1998, pp. 861866.