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Volumn 30, Issue 5, 2011, Pages 637-650

Mapping multi-domain applications onto coarse-grained reconfigurable architectures

Author keywords

Design automation; high level synthesis; parallelizing compiler; reconfigurable architecture

Indexed keywords

3D GRAPHICS; COARSE GRAINED RECONFIGURABLE ARCHITECTURE; DESIGN AUTOMATIONS; FLOATING POINT OPERATIONS; FLOATING-POINT ARITHMETIC; HEURISTIC MAPPING; HIGH-LEVEL SYNTHESIS; INTEGER ARITHMETIC; INTEGER LINEAR PROGRAMMING; LOGICAL OPERATIONS; MAPPING APPLICATIONS; MULTI DOMAINS; OPTIMAL FORMULATION; OPTIMAL MAPPING; PARALLELIZING COMPILER; PERFORMANCE IMPROVEMENTS; RECONFIGURABLE ARCHITECTURE; SOFTWARE IMPLEMENTATION;

EID: 79955379964     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2010.2098571     Document Type: Article
Times cited : (53)

References (29)
  • 1
    • 0034187952 scopus 로고    scopus 로고
    • Morphosys: An integrated reconfigurable system for dataparallel and computation-intensive applications
    • May
    • H. Singh, M.-H. Lee, G. Lu, F. J. Kurdahi, N. Bagherzadeh, and E. M. C. Filho, "Morphosys: An integrated reconfigurable system for dataparallel and computation-intensive applications," IEEE Trans. Comput., vol. 49, no. 5, pp. 465-481, May 2000.
    • (2000) IEEE Trans. Comput. , vol.49 , Issue.5 , pp. 465-481
    • Singh, H.1    Lee, M.-H.2    Lu, G.3    Kurdahi, F.J.4    Bagherzadeh, N.5    Filho, E.M.C.6
  • 2
    • 84870442968 scopus 로고    scopus 로고
    • PACT XPP, [Online]. Available
    • PACT XPP Technologies [Online]. Available: http://www.pactxpp.com
    • Technologies
  • 3
    • 35248884474 scopus 로고    scopus 로고
    • ADRES: An architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix
    • B. Mei, S. Vernalde, D. Verkest, H. D. Man, and R. Lauwereins, "ADRES: An architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix," in Proc. FPLA, 2003, pp. 61-70.
    • (2003) Proc. FPLA , pp. 61-70
    • Mei, B.1    Vernalde, S.2    Verkest, D.3    Man, H.D.4    Lauwereins, R.5
  • 4
    • 4243704325 scopus 로고    scopus 로고
    • [Online]. Available
    • Chameleon Systems, Inc. [Online]. Available: http://www.chameleonsystems. Com
    • Chameleon Systems Inc.
  • 5
    • 84956862926 scopus 로고    scopus 로고
    • Instruction-Level Parallelism for Reconfigurable Computing
    • Field-Programmable Logic and Applications: From PFGAs to Computing Paradigm
    • T. J. Callahan and J. Wawrzynek, "Instruction-level parallelism for reconfigurable computing," in Proc. IWFPL, 1998, pp. 248-257. (Pubitemid 128125221)
    • (1998) Lecture Notes in Computer Science , Issue.1482 , pp. 248-257
    • Callahan, T.J.1    Wawrzynek, J.2
  • 7
    • 84962791602 scopus 로고    scopus 로고
    • DRESC: A retargetable compiler for coarse-grained reconfigurable architectures
    • Dec
    • B. Mei, S. Vernalde, D. Verkest, H. D. Man, and R. Lauwereins, "DRESC: A retargetable compiler for coarse-grained reconfigurable architectures," in Proc. ICFPT, Dec. 2002, pp. 166-173.
    • (2002) Proc. ICFPT , pp. 166-173
    • Mei, B.1    Vernalde, S.2    Verkest, D.3    Man, H.D.4    Lauwereins, R.5
  • 8
    • 46149124804 scopus 로고    scopus 로고
    • High-level synthesis challenges and solutions for a dynamically reconfigurable processor
    • Nov
    • T. Toi, N. Nakamura, Y. Kato, T. Awashima, K. Wakabayashi, and L. Jing, "High-level synthesis challenges and solutions for a dynamically reconfigurable processor," in Proc. ICCAD, Nov. 2006, pp. 702-708.
    • (2006) Proc. ICCAD , pp. 702-708
    • Toi, T.1    Nakamura, N.2    Kato, Y.3    Awashima, T.4    Wakabayashi, K.5    Jing, L.6
  • 9
    • 63549126166 scopus 로고    scopus 로고
    • Edgecentric modulo scheduling for coarse-grained reconfigurable architectures
    • Oct
    • H. Park, K. Fan, S. A. Mahlke, T. Oh, H. Kim, and H. Kim, "Edgecentric modulo scheduling for coarse-grained reconfigurable architectures," in Proc. PACT, Oct. 2008, pp. 166-176.
    • (2008) Proc. PACT , pp. 166-176
    • Park, H.1    Fan, K.2    Mahlke, S.A.3    Oh, T.4    Kim, H.5    Kim, H.6
  • 11
    • 70350622992 scopus 로고    scopus 로고
    • A graph drawing based spatial mapping algorithm for coarse-grained reconfigurable architecture
    • Jun
    • J. Yoon, A. Shrivastava, S. Park, M. Ahn, and Y. Paek, "A graph drawing based spatial mapping algorithm for coarse-grained reconfigurable architecture," IEEE Trans. Very Large Scale Integr. Syst., vol. 17, no. 11, pp. 1565-1578, Jun. 2008.
    • (2008) IEEE Trans. Very Large Scale Integr. Syst. , vol.17 , Issue.11 , pp. 1565-1578
    • Yoon, J.1    Shrivastava, A.2    Park, S.3    Ahn, M.4    Paek, Y.5
  • 13
    • 33646918066 scopus 로고    scopus 로고
    • Resource sharing and pipelining in coarse-grained reconfigurable architecture for domainspecific optimization
    • Y. Kim, M. Kiemb, C. Park, J. Jung, and K. Choi, "Resource sharing and pipelining in coarse-grained reconfigurable architecture for domainspecific optimization," in Proc. DATE, Mar. 2005, pp. 12-17.
    • (2005) Proc. DATE Mar. , pp. 12-17
    • Kim, Y.1    Kiemb, M.2    Park, C.3    Jung, J.4    Choi, K.5
  • 14
    • 34247258357 scopus 로고    scopus 로고
    • Power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architecture
    • DOI 10.1145/1165573.1165646, ISLPED'06 - Proceedings of the 2006 International Symposium on Low Power Electronics and Design
    • Y. Kim, I. Park, K. Choi, and Y. Paek, "Power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architecture," in Proc. ISLPED, Oct. 2006, pp. 310-315. (Pubitemid 46609755)
    • (2006) Proceedings of the International Symposium on Low Power Electronics and Design , vol.2006 , pp. 310-315
    • Kim, Y.1    Park, I.2    Choi, K.3    Paek, Y.4
  • 15
    • 0343051708 scopus 로고    scopus 로고
    • [Online]. Available
    • The SUIF Compiler System [Online]. Available: http://suif.stanford.edu
    • The SUIF Compiler System
  • 17
    • 69949103700 scopus 로고    scopus 로고
    • Automatic mapping of application to coarse-grained reconfigurable architecture based on high-level synthesis techniques
    • Nov
    • G. Lee, S. Lee, and K. Choi, "Automatic mapping of application to coarse-grained reconfigurable architecture based on high-level synthesis techniques," in Proc. ISOCC, Nov. 2008, pp. 395-398.
    • (2008) Proc. ISOCC , pp. 395-398
    • Lee, G.1    Lee, S.2    Choi, K.3
  • 18
    • 2442617141 scopus 로고    scopus 로고
    • Quantum-inspired evolutionary algorithms with a new termination criterion, Hε Gate, and two phase scheme
    • Apr
    • K. Han and J. Kim, "Quantum-inspired evolutionary algorithms with a new termination criterion, Hε gate, and two phase scheme," IEEE Trans. Evol. Computat., vol. 8, no. 2, pp. 156-169, Apr. 2004.
    • (2004) IEEE Trans. Evol. Computat. , vol.8 , Issue.2 , pp. 156-169
    • Han, K.1    Kim, J.2
  • 19
    • 57349104476 scopus 로고    scopus 로고
    • [Online]. Available
    • GNU Linear Programming Kit [Online]. Available: http://www.gnu.org/ software/glpk
    • GNU Linear Programming Kit
  • 20
    • 77951261673 scopus 로고    scopus 로고
    • Routing-aware application mapping considering Steiner point for coarse-grained reconfigurable architecture
    • G. Lee, S. Lee, K. Choi, and N. Dutt, "Routing-aware application mapping considering Steiner point for coarse-grained reconfigurable architecture," in Proc. ARC, 2010, pp. 231-243.
    • (2010) Proc. ARC , pp. 231-243
    • Lee, G.1    Lee, S.2    Choi, K.3    Dutt, N.4
  • 21
    • 51049094641 scopus 로고    scopus 로고
    • Implementation of floating-point operations for 3-D graphics on a coarse-grained reconfigurable architecture
    • Sep
    • M. Jo, V. K. P. Arava, H. Yang, and K. Choi, "Implementation of floating-point operations for 3-D graphics on a coarse-grained reconfigurable architecture," in Proc. IEEE-SOCC, Sep. 2007, pp. 127-130.
    • (2007) Proc. IEEE-SOCC , pp. 127-130
    • Jo, M.1    Arava, V.K.P.2    Yang, H.3    Choi, K.4
  • 24
    • 77954787580 scopus 로고    scopus 로고
    • Design heuristics for mapping floating-point scientific computational kernels onto high performance reconfigurable computers
    • Jun
    • J. L. Rice, K. H. Abed, and G. R. Morris, "Design heuristics for mapping floating-point scientific computational kernels onto high performance reconfigurable computers," J. Comput., vol. 4, no. 6, pp. 542-553, Jun. 2009.
    • (2009) J. Comput. , vol.4 , Issue.6 , pp. 542-553
    • Rice, J.L.1    Abed, K.H.2    Morris, G.R.3
  • 26
    • 49749083963 scopus 로고    scopus 로고
    • Architecture exploration of NAND flashbased multimedia card
    • Mar
    • S. Kim, C. Park, and S. Ha, "Architecture exploration of NAND flashbased multimedia card," in Proc. DATE, Mar. 2008, pp. 218-223.
    • (2008) Proc. DATE , pp. 218-223
    • Kim, S.1    Park, C.2    Ha, S.3
  • 27
    • 70350075833 scopus 로고    scopus 로고
    • On-chip communication architecture exploration for processor-pool-based MPSoC
    • Apr
    • Y. Joo, S. Kim, and S. Ha, "On-chip communication architecture exploration for processor-pool-based MPSoC," in Proc. DATE, Apr. 2009, pp. 466-471.
    • (2009) Proc. DATE , pp. 466-471
    • Joo, Y.1    Kim, S.2    Ha, S.3
  • 28
    • 70350055226 scopus 로고    scopus 로고
    • Pipelined data parallel task mapping/scheduling technique for MPSoC
    • Apr
    • H. Yang and S. Ha, "Pipelined data parallel task mapping/scheduling technique for MPSoC," in Proc. DATE, Apr. 2009, pp. 69-74.
    • (2009) Proc. DATE , pp. 69-74
    • Yang, H.1    Ha, S.2
  • 29
    • 79955368639 scopus 로고    scopus 로고
    • [Online]. Available
    • Synopsys Corporation [Online]. Available: http://www.synopsys.com
    • Synopsys Corporation


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.