메뉴 건너뛰기




Volumn 49, Issue 5, 2000, Pages 465-481

MorphoSys: An integrated reconfigurable system for data-parallel and computation-intensive applications

Author keywords

[No Author keywords available]

Indexed keywords

MOVING PICTURE EXPERTS GROUP (MPEG) STANDARDS; RECONFIGURABLE COMPUTING SYSTEMS; SINGLE INSTRUCTION MULTIPLE DATA (SIMD);

EID: 0034187952     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.859540     Document Type: Article
Times cited : (748)

References (37)
  • 1
    • 0030171884 scopus 로고    scopus 로고
    • Architecture of FPGAs and CPLDs: A Tutorial
    • S. Brown and J. Rose, "Architecture of FPGAs and CPLDs: A Tutorial," IEEE Design and Test of Computers, vol. 13, no. 2, pp. 42-57, 1996.
    • (1996) IEEE Design and Test of Computers , vol.13 , Issue.2 , pp. 42-57
    • Brown, S.1    Rose, J.2
  • 2
    • 0026964221 scopus 로고
    • Reconfigurable Multi-Processor IC for Rapid Prototyping of Algorithmic-Specific High-Speed Data-paths
    • Dec.
    • D. Chen and J. Rabaey, "Reconfigurable Multi-Processor IC for Rapid Prototyping of Algorithmic-Specific High-Speed Data-paths," IEEE J. Solid-State Circuits, vol. 27, no. 12, Dec. 1992.
    • (1992) IEEE J. Solid-State Circuits , vol.27 , Issue.12
    • Chen, D.1    Rabaey, J.2
  • 4
    • 0030394522 scopus 로고    scopus 로고
    • MATRIX: A Reconfigurable Computing Architecture with Configurable Instruction Distribution and Deployable Resources
    • Apr.
    • E. Mirsky and A. DeHon, "MATRIX: A Reconfigurable Computing Architecture with Configurable Instruction Distribution and Deployable Resources," Proc. IEEE Symp. FPGAs for Custom-Computing Machines, pp. 157-166, Apr. 1996.
    • (1996) Proc. IEEE Symp. FPGAs for Custom-Computing Machines , pp. 157-166
    • Mirsky, E.1    DeHon, A.2
  • 10
    • 0042280401 scopus 로고
    • Introduction to Programmable Active Memories
    • Prentice Hall
    • P. Bertin, D. Roncin, and J. Vuillemin, "Introduction to Programmable Active Memories," Systolic Array Processors, pp. 300-309, Prentice Hall, 1989.
    • (1989) Systolic Array Processors , pp. 300-309
    • Bertin, P.1    Roncin, D.2    Vuillemin, J.3
  • 11
    • 0029252159 scopus 로고
    • A 2.4 GOPS Data-Driven Reconfigurable Multiprocessor IC for DSP
    • Feb.
    • A.K. Yeung and J.M. Rabaey, "A 2.4 GOPS Data-Driven Reconfigurable Multiprocessor IC for DSP," Proc. IEEE Solid-State Circuits Conf., pp. 108-109, 346, 440, Feb. 1995.
    • (1995) Proc. IEEE Solid-State Circuits Conf. , pp. 108-109
    • Yeung, A.K.1    Rabaey, J.M.2
  • 14
    • 0343051708 scopus 로고    scopus 로고
    • The Stanford SUIF Compiler Group, "SUIF Compiler System," http://suif.stanford.edu.
    • SUIF Compiler System
  • 17
    • 0026883789 scopus 로고
    • VLSI Architecture for Block-Matching Motion Estimation Algorithm
    • June
    • C. Hsieh and T. Lin, "VLSI Architecture for Block-Matching Motion Estimation Algorithm," IEEE Trans. Circuits and Systems for Video Technology, vol. 2, no. 2, pp. 169-175, June 1992.
    • (1992) IEEE Trans. Circuits and Systems for Video Technology , vol.2 , Issue.2 , pp. 169-175
    • Hsieh, C.1    Lin, T.2
  • 18
    • 0028699877 scopus 로고
    • A VLSI Design for Full Search Block Matching Motion Estimation
    • Sept.
    • S.H. Nam, J.S. Baek, T.Y. Lee, and M.K. Lee, "A VLSI Design for Full Search Block Matching Motion Estimation," Proc. IEEE ASIC Conf., pp. 254-257, Sept. 1994.
    • (1994) Proc. IEEE ASIC Conf. , pp. 254-257
    • Nam, S.H.1    Baek, J.S.2    Lee, T.Y.3    Lee, M.K.4
  • 19
    • 0024755322 scopus 로고
    • A Family of VLSI Designs for Motion Compensation Block Matching Algorithm
    • Oct.
    • K.-M. Yang, M.-T. Sun, and L. Wu, "A Family of VLSI Designs for Motion Compensation Block Matching Algorithm," IEEE Trans. Circuits and Systems, vol. 36, no. 10, pp. 1,317-1,325, Oct. 1989.
    • (1989) IEEE Trans. Circuits and Systems , vol.36 , Issue.10
    • Yang, K.-M.1    Sun, M.-T.2    Wu, L.3
  • 21
    • 0017538003 scopus 로고
    • A Fast Computational Algorithm for the Discrete Cosine Transform
    • Sept.
    • W.-H. Chen, C.H. Smith, and S.C. Fralick, "A Fast Computational Algorithm for the Discrete Cosine Transform," IEEE Trans. Comm., vol. 25, no. 9, pp. 1,004-1,009, Sept. 1977.
    • (1977) IEEE Trans. Comm. , vol.25 , Issue.9
    • Chen, W.-H.1    Smith, C.H.2    Fralick, S.C.3
  • 22
    • 0032027434 scopus 로고    scopus 로고
    • V830R/AV: Embedded Multimedia Superscalar RISC Processor
    • Mar./Apr.
    • T. Arai, I. Kuroda, K. Nadehara, and K. Suzuki, "V830R/AV: Embedded Multimedia Superscalar RISC Processor," IEEE Micro, pp. 36-47, Mar./Apr. 1998.
    • (1998) IEEE Micro , pp. 36-47
    • Arai, T.1    Kuroda, I.2    Nadehara, K.3    Suzuki, K.4
  • 24
    • 84866837651 scopus 로고    scopus 로고
    • Defense and Advanced Research Projects Agency (DARPA), "Challenges for Adaptive Computing Systems," http://www. darpa.mil/ito/research/acs/challenges.html.
    • Challenges for Adaptive Computing Systems
  • 30
    • 33749927105 scopus 로고    scopus 로고
    • Other Block Ciphers
    • New York: John Wiley
    • B. Schneier, "Other Block Ciphers," Applied Cryptography, pp. 319-325, New York: John Wiley, 1996.
    • (1996) Applied Cryptography , pp. 319-325
    • Schneier, B.1
  • 31
    • 0031632579 scopus 로고    scopus 로고
    • HiPCrypto: A High Performance VLSI Cryptographic Chip
    • Sept.
    • S. Salomao, V. Alves, and B.C. Filho, "HiPCrypto: A High Performance VLSI Cryptographic Chip," Proc. IEEE ASIC Conf., pp. 7-13, Sept. 1998.
    • (1998) Proc. IEEE ASIC Conf. , pp. 7-13
    • Salomao, S.1    Alves, V.2    Filho, B.C.3
  • 33
    • 0019055071 scopus 로고
    • Design of Massively Parallel Processor
    • Sept.
    • K.E Batcher, "Design of Massively Parallel Processor," IEEE Trans. Computers, vol. 29, no. 9, pp. 836-840, Sept. 1980.
    • (1980) IEEE Trans. Computers , vol.29 , Issue.9 , pp. 836-840
    • Batcher, K.E.1
  • 35
    • 0033345080 scopus 로고    scopus 로고
    • REMARC: Reconfigurable Multimedia Array Co-Processor
    • Feb.
    • T. Miyamori and K. Olukotun, "REMARC: Reconfigurable Multimedia Array Co-Processor," IEICE Trans. Information Systems, vol. E82-D, no. 2, pp. 389-397, Feb. 1999.
    • (1999) IEICE Trans. Information Systems , vol.E82-D , Issue.2 , pp. 389-397
    • Miyamori, T.1    Olukotun, K.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.