A graph drawing based spatial mapping algorithm for coarse-grained reconfigurable architectures

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 17, Issue 11, 2009, Pages 1565-1578

  Yoon, Jonghee W ^a   Shrivastava, Aviral ^b   Park, Sanghyun ^a   Ahn, Minwook ^a   Paek, Yunheung ^a  

^a Seoul National University   (South Korea)

^b AZ 85281   (United States)

Author keywords

Compiler; Kernel mapping; Reconfigurable architecture

Indexed keywords

COARSE GRAINED RECONFIGURABLE ARCHITECTURE; COMPILER; EXECUTION CYCLES; GRAPH DRAWING; INTERCONNECTION TOPOLOGIES; KERNEL MAPPING; MAPPING APPLICATIONS; MEDIABENCH; PERFORMANCE IMPROVEMENTS; PERFORMANCE OPTIMIZATIONS; POWER CONSUMPTION; PROCESSING ELEMENTS; RECONFIGURABLE ARCHITECTURE; SHARED RESOURCES; SPATIAL MAPPING; SYNTHETIC APPLICATION;

CONFORMAL MAPPING; DRAWING (GRAPHICS); MULTIMEDIA SYSTEMS; TOPOLOGY;

PROGRAM COMPILERS;

EID: 70350622992     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2008.2001746     Document Type: Article

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