Power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architecture

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn 2006, Issue , 2006, Pages 310-315

  Kim, Yoonjin ^a   Park, Ilhyun ^a   Choi, Kiyoung ^a   Paek, Yunheung ^a  

^a Seoul National University   (South Korea)

Author keywords

Coarse grained reconfigurable architecture (CGRA); Configuration cache; Context pipelining; Loop pipelining; Low power; Spatial mapping; System on chip (SoC); Temporal mapping

Indexed keywords

CACHE MEMORY; ELECTRIC POWER UTILIZATION; EMBEDDED SYSTEMS; PROGRAM PROCESSORS;

COARSE-GRAINED RECONFIGURABLE ARCHITECTURE (CGRA); CONFIGURATION CACHE; CONTEXT PIPELINING; LOOP PIPELINING; SPATIAL MAPPING; SYSTEM-ON-CHIP (SOC); TEMPORAL MAPPING;

COMPUTER ARCHITECTURE;

EID: 34247258357     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1165573.1165646     Document Type: Conference Paper

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