On-chip communication architecture exploration for processor-pool-based MPSoC

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2009, Pages 466-471

  Joo, Young Pyo ^a   Sungchan, Kim ^a   Soonhoi, Ha ^a  

^a Seoul National University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION-SPECIFIC OPTIMIZATIONS; AREA REQUIREMENT; BANDWIDTH ANALYSIS; CLOCK FREQUENCY; DESIGN SPACES; EARLY PRUNING; EFFICIENT ARCHITECTURE; NON-TRIVIAL TASKS; ON CHIP COMMUNICATION; ON-CHIP NETWORKS; PARETO OPTIMAL SOLUTIONS; SYSTEMATIC METHODOLOGY; TASK EXECUTIONS;

COMPUTER SIMULATION; DESIGN; ELECTRIC NETWORK TOPOLOGY; PUMPING PLANTS;

COMPUTER ARCHITECTURE;

EID: 70350075833     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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