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Volumn , Issue , 2006, Pages 702-708

High-level synthesis challenges and solutions for a dynamically reconfigurable processor

Author keywords

Dynamic reconfiguration; High level synthesis; Reconfigurable processor

Indexed keywords

(U ,V) OPERATOR; ACCURATE TIMING; APPLICATION-SPECIFIC INTEGRATED CIRCUIT (ASIC); BEHAVIORAL-SYNTHESIS; CLOCK SPEEDS; COARSE GRAINING; COMPUTER-AIDED DESIGN; CONTEXT ARCHITECTURE; DATA PATHS; DYNAMICALLY RECONFIGURABLE PROCESSOR (DRP); EXPERIMENTAL RESULTS; FINITE STATE MACHINE (FSM); HIGH AREA EFFICIENCY; HIGH LEVEL SYNTHESIS (HLS); INTERNATIONAL CONFERENCES; PROCESSING ELEMENTS (PES); RE-CONFIGURABLE; REGISTER SHARING; SPATIAL DIMENSIONS; STORAGE UNITS; TIME-MULTIPLEXED; WIRE DELAYS;

EID: 46149124804     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2006.320016     Document Type: Conference Paper
Times cited : (44)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.