Design heuristics for mapping floating-point scientific computational kernels onto high performance reconfigurable computers

Journal of Computers

Volumn 4, Issue 6, 2009, Pages 542-553

  Rice, Justin L ^a   Abed, Khalid H ^a   Morris, Gerald R ^a  

^a Jackson State University   (United States)

Author keywords

Algorithm mapping; Field programmable gate array (FPGA); High performance reconfigurable computer (HPRC)

Indexed keywords

COMPUTER CIRCUITS; DIGITAL ARITHMETIC; GENERAL PURPOSE COMPUTERS; INTEGRATED CIRCUIT DESIGN; LOGIC GATES; MAPPING; RECONFIGURABLE HARDWARE; SIGNAL RECEIVERS;

APPLICATION MODULE; COMPUTATIONAL KERNELS; DESIGN HEURISTICS; DEVELOPMENT FLOW; FLOATING POINTS; FLOATING-POINT CALCULATIONS; GENERAL PURPOSE PROCESSORS; RECONFIGURABLE COMPUTER;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 77954787580     PISSN: 1796203X     EISSN: None     Source Type: Journal    
DOI: 10.4304/jcp.4.6.542-553     Document Type: Article

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