SPR: An architecture-adaptive CGRA mapping tool

Proceedings of the 7th ACM SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA'09

Volumn , Issue , 2009, Pages 191-200

  Friedman, Stephen ^a   Carroll, Allan ^a   Van Essen, Brian ^a   Ylvisaker, Benjamin ^a   Ebeling, Carl ^a   Hauck, Scott ^a  

^a University of Washington   (United States)

Author keywords

Algorithms; Design; Experimentation; Performance

Indexed keywords

ARCHITECTURE-ADAPTIVE; CHANNEL WIDTHS; COARSE GRAINED RECONFIGURABLE ARCHITECTURE; CONFIGURABLE; DYNAMIC CLUSTERING METHODS; EXPERIMENTATION; FIXED FREQUENCY; MAPPING TOOLS; PATHFINDER ALGORITHM; PERFORMANCE; TIME MULTIPLEXED;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); LOGIC GATES; MULTIPLEXING; SURFACE PLASMON RESONANCE; VERY LONG INSTRUCTION WORD ARCHITECTURE;

ROUTING ALGORITHMS;

EID: 67650694666     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1508128.1508158     Document Type: Conference Paper

References (20)

1. Electric VLSI Design System. Sun Microsystems and Static Free Software. http://www.staticfreesoft.com/.
2. Mosaic Research Group. http://www.cs.washington.edu/research/lis/mosaic/.
3. V. Betz and J. Rose. VPR: A New Packing, Placement and Routing Tool for FPGA Research. In International Workshop on Field-Programmable Logic and Applications, 1997.
4. A. Carroll and C. Ebeling. Reducing the Space Complexity of Pipelined Routing Using Modified Range Encoding. In International Conference on Field-Programmable Logic and Applications, 2006.
5. A. Carroll, S. Friedman, B. Van Essen, A. Wood, B. Ylvisaker, C. Ebeling, and S. Hauck. Designing a Coarse-grained Reconfigurable Architecture for Power Efficiency. Technical report, Department of Energy NA-22 University Information Technical Interchange Review Meeting, 2007.
6. C. Ebeling, D. C. Cronquist, and P. Franklin. RaPiD - Reconfigurable Pipelined Datapath. In International Workshop on Field-Programmable Logic and Applications, pages 126-135, 1996. (Pubitemid 126136669) (Pubitemid 126136669)
7. K. Eguro and S. Hauck. Armada: Timing-driven Pipeline-aware Routing for FPGAs. In ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pages 169-178, 2006. (Pubitemid 44032250) (Pubitemid 44032250)
8. S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi. Optimization by Simulated Annealing. Science, 220:671-680, 1983.
9. J.-e. Lee, K. Choi, and N. Dutt. Compilation Approach for Coarse-grained Reconfigurable Architectures. IEEE Design & Test of Computers, 20(1):26-33, 2003.
10. S. Li and C. Ebeling. QuickRoute: A Fast Routing Algorithm for Pipelined Architectures. In IEEE International Conference on Field-Programmable Technology, pages 73-80, 2004. (Pubitemid 40859484) (Pubitemid 40859484)
11. L. McMurchie and C. Ebeling. PathFinder: A Negotiation-based Performance-driven Router for FPGAs. In ACM International Symposium on Field-Programmable Gate Arrays, pages 111-117, 1995.
12. B. Mei, S. Vernalde, D. Verkest, H. De Man, and R. Lauwereins. DRESC: A Retargetable Compiler for Coarse-grained Reconfigurable Architectures. In IEEE International Conference on Field-Programmable Technology, pages 166-173, 2002.
13. B. Mei, S. Vernalde, D. Verkest, H. De Man, and R. Lauwereins. ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix. In International Conference on Field-Programmable Logic and Applications, volume 2778, pages 61-70, 2003.
14. E. Mirsky and A. DeHon. MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources. In IEEE Symposium on Field-Programmable Custom Computing Machines, pages 157-166, 1996.
15. M. Mishra and S. C. Goldstein. Virtualization on the Tartan Reconfigurable Architecture. In International Conference on Field-Programmable Logic and Applications, pages 323-330, 2007.
16. B. R. Rau. Iterative Modulo Scheduling: An Algorithm for Software Pipelining Loops. In International Symposium on Microarchitecture, pages 63-74, 1994
17. A. Sharma, S. Hauck, and C. Ebeling. Architecture-adaptive Routability-driven Placement for FPGAs. In International Conference on Field-Programmable Logic and Applications, pages 427-432, 2005. (Pubitemid 44183469) (Pubitemid 44183469)
18. H. Singh, M.-H. Lee, G. Lu, F. Kurdahi, N. Bagherzadeh, and E. Chaves Filho. MorphoSys: An Integrated Reconfigurable System for Data-parallel and Computation-Intensive Applications. IEEE Transactions on Computers, 49(5):465-481, 2000. (Pubitemid 30897141)
19. W. Tsu, K. Macy, A. Joshi, R. Huang, N. Walker, T. Tung, O. Rowhani, V. George, J. Wawrzynek, and A. DeHon. HSRA: High-speed, Hierarchical Synchronous Reconfigurable Array. In ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pages 125-134, 1999.
20. S. J. Wilton. Architecture and Algorithms for Field-Programmable Gate Arrays with Embedded Memory. PhD thesis, University of Toronto, 1997.