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Volumn 1, Issue , 2008, Pages

Automatic mapping of application to coarse-grained reconfigurable architecture based on high-level synthesis techniques

Author keywords

Coarse grained reconfigurable architecture; Highlevel synthesis; Mapping

Indexed keywords

AUTOMATIC MAPPING; COARSE-GRAINED RECONFIGURABLE ARCHITECTURE; HIGHLEVEL SYNTHESIS; LOOP PIPELINING; LOOP UNROLLING; MAPPING APPLICATIONS; PERFORMANCE ENHANCING; RECONFIGURABLE ARRAY; TEMPORAL MAPPINGS;

EID: 69949103700     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOCDC.2008.4815655     Document Type: Conference Paper
Times cited : (9)

References (13)
  • 1
    • 0034187952 scopus 로고    scopus 로고
    • MorphoSys: An integrated reconfigurable system for data-parallel and computation-intensive applications
    • DOI 10.1109/12.859540
    • H. Singh, M.-H. Lee, G. Lu, F. J. Kurdahi, N. Bagherzadeh, and E. M. C. Filho, "Morphosys: an integrated reconfigurable system for dataparallel and computation-intensive applications," IEEE Trans. on Computers, vol.49, pp. 465-481, May 2000. (Pubitemid 30897141)
    • (2000) IEEE Transactions on Computers , vol.49 , Issue.5 , pp. 465-481
    • Singh, H.1    Lee, M.-H.2    Lu, G.3    Kurdahi, F.J.4    Bagherzadeh, N.5    Chaves Filho, E.M.6
  • 3
    • 17844392445 scopus 로고    scopus 로고
    • ADRES: An architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix
    • B. Mei, S. Vernalde, D. Verkest, H. D. Man, and R. Lauwereins, "ADRES: An architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix," in Proc. of FPLA 2003.
    • (2003) Proc. of FPLA
    • Mei, B.1    Vernalde, S.2    Verkest, D.3    Man, H.D.4    Lauwereins, R.5
  • 7
    • 84962791602 scopus 로고    scopus 로고
    • DRESC: A retargetable compiler for coarse-grained reconfigurable architectures
    • B. Mei, S. Vernalde, D. Verkest, H.D. Man, and R. Lauwereins, "DRESC: A retargetable compiler for coarse-grained reconfigurable architectures," in Proc. of ICFPT, 2002.
    • (2002) Proc. of ICFPT
    • Mei, B.1    Vernalde, S.2    Verkest, D.3    Man, H.D.4    Lauwereins, R.5
  • 8
  • 9
    • 69949103243 scopus 로고    scopus 로고
    • DSPStone benchmark, http://www.iss.rwthaachen.de/projekte/Tools/DSPSTONE/ dspstone.html.
    • DSPStone Benchmark
  • 10
    • 33646918066 scopus 로고    scopus 로고
    • Resource sharing and pipelining in coarse-grained reconfigurable architecture for domainspecific optimization
    • Y. Kim, M. Kiemb, C. Park, J. Jung, and K. Choi, "Resource sharing and pipelining in coarse-grained reconfigurable architecture for domainspecific optimization," in Proc. of DATE, 2005.
    • (2005) Proc. of DATE
    • Kim, Y.1    Kiemb, M.2    Park, C.3    Jung, J.4    Choi, K.5
  • 11
    • 34247258357 scopus 로고    scopus 로고
    • Power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architecture
    • Y. Kim, I. Park, K. Choi, and Y. Paek, "Power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architecture," in Proc. of ISLPED, 2006.
    • (2006) Proc. of ISLPED
    • Kim, Y.1    Park, I.2    Choi, K.3    Paek, Y.4
  • 13
    • 2442617141 scopus 로고    scopus 로고
    • Quantum-inspired evolutionary algorithms with a new termination criterion, Hεgate, and two phase scheme
    • Apr.
    • K. Han and J. Kim, "Quantum-inspired evolutionary algorithms with a new termination criterion, Hεgate, and two phase scheme," in IEEE Transactions on Evolutionary Computation 8, Apr. 2004.
    • (2004) IEEE Transactions on Evolutionary Computation 8
    • Han, K.1    Kim, J.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.