Resource sharing and pipelining in coarse-grained reconfigurable architecture for domain-specific optimization

Proceedings -Design, Automation and Test in Europe, DATE '05

Volumn I, Issue , 2005, Pages 12-17

  Kim, Yoonjin ^a   Kiemb, Mary ^a   Park, Chulsoo ^a   Jung, Jinyong ^a   Choi, Kiyoung ^a  

^a Seoul National University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ARRAYS; OPTIMIZATION; PROGRAM PROCESSORS; RESOURCE ALLOCATION;

DESIGN SPACE EXPLORATION; FUNCTIONAL RESOURCES; PIPELINING; RECONFIGURABLE ARRAY ARCHITECTURE;

COMPUTER ARCHITECTURE;

EID: 33646918066     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2005.260     Document Type: Conference Paper

References (10)

1. Reiner Hartenstein, "A decade of reconfigurable computing: a visionary retrospective," in Proc. of DATE, 2001.
2. Hartej Singh, Ming-Hau Lee, Guangming Lu, Fadi J. Kurdahi, Nader Bagherzadeh, and Eliseu M. Chaves Filho, "MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications," IEEE Trans. on Computers, vol. 49, no. 5, pp. 465-481, May 2000.
3. Jurgen Becker and Martin Vorbach, "Architecture, memory and interface technology integration of an industrial/academic configurable system-on-chip (CSoC)," in Proc. of ISVLSI, 2003.
4. Bingfeng Mei, Serge Vernalde, Diederik Verkest, and Rudy Lauwereins, "Design methodology for a tightly coupled VLIW/reconfigurable matrix architecture: a case study," in Proc. of DATE, 2004.
5. Reiner Hartenstein, M. Herz, T. Hoffmann, and U. Nageldinger, "KressArray Xplorer: a new CAD environment to optimize reconfigurable datapath array architectures," in Proc. of ASP-DAC, 2000.
6. Nikhil Bansal, Sumit Gupta, Nikil D. Dutt, and Alex Nicolau, "Analysis of the performance of coarse-grain reconfigurable architectures with different processing element Configurations," in Proc. of WASP, 2003.
7. Jong-eun Lee, Kiyoung Choi, and Nikil D. Dutt, "Mapping loops on coarse-grain reconfigurable architectures using memory operation sharing," in Technical Report 02-34, Center for Embedded Computer Systems(CECS), Univ. of California, Irvine, Calif., 2002.
8. Jong-eun Lee, Kiyoung Choi, and Nikil D. Dutt, "An algorithm for mapping loops onto coarse-grained reconfigurable architectures," in Proc. of LCTES, 2003.
9. Synplicity Corp.: http://www.synplicity.com
10. Xilinx Corp.: http://www.xilinx.com