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Volumn 1482, Issue , 1998, Pages 248-257

Instruction-level parallelism for reconfigurable computing

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION PROGRAMS; COMPUTATION THEORY; COMPUTER CIRCUITS; COPROCESSOR; INDUCTIVE LOGIC PROGRAMMING (ILP); RECONFIGURABLE ARCHITECTURES; VERY LONG INSTRUCTION WORD ARCHITECTURE;

EID: 84956862926     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/bfb0055252     Document Type: Conference Paper
Times cited : (41)

References (16)
  • 1
    • 0028737764 scopus 로고
    • An Asynchronous Approach to Efficient Execution of Programs on Adaptive Architectures Utilizing FPGAs
    • IEEE Comput. Soc. Press,. AN4754552
    • L. Agarwal, M. Wazlowski, and S. Ghosh. An Asynchronous Approach to Efficient Execution of Programs on Adaptive Architectures Utilizing FPGAs. In Proceedings IEEE Workshop on FPGAs for Custom Computing Machines, pages 101-10. IEEE Comput. Soc. Press, 1994. AN4754552.
    • (1994) Proceedings IEEE Workshop on FPGAs for Custom Computing Machines , pp. 101-110
    • Agarwal, L.1    Wazlowski, M.2    Ghosh, S.3
  • 4
    • 0028738226 scopus 로고
    • DPGA-Coupled Microprocessors: Commodity ICs for the Early 21st Century
    • IEEE Comput. Soc. Press
    • A. DeHon. DPGA-Coupled Microprocessors: Commodity ICs for the Early 21st Century. In Proceedings IEEE Workshop on FPGAs for Custom Computing Machines, pages 31-9. IEEE Comput. Soc. Press, 1994.
    • (1994) Proceedings IEEE Workshop on FPGAs for Custom Computing Machines , pp. 31-39
    • DeHon, A.1
  • 7
    • 84949190938 scopus 로고
    • Instruction-Level Parallel Processing
    • IEEE Computer Society Press,. H.C. Torng and S. Vassiliadis, editors
    • J.A. Fisher and B.R. Rau. Instruction-Level Parallel Processing. In H.C. Torng and S. Vassiliadis, editors, Instruction-Level Parallel Processors, pages 41-49. IEEE Computer Society Press, 1995.
    • (1995) Instruction-Level Parallel Processors , pp. 41-49
    • Fisher, J.A.1    Rau, B.R.2
  • 8
    • 84956863164 scopus 로고
    • Data parallel C on a reconfigurable logic array
    • M. Gokhale and B. Schott. Data parallel C on a reconfigurable logic array. Journal of Supercomputing, pages 1-24, 1994.
    • (1994) Journal of Supercomputing , pp. 1-24
    • Gokhale, M.1    Schott, B.2
  • 12
    • 0344506824 scopus 로고    scopus 로고
    • The Flow Analysis and Transformation Libraries of Machine SUIF
    • Aug
    • G. Holloway and C. Young. The Flow Analysis and Transformation Libraries of Machine SUIF. In Proceedings of the Second SUIF Compiler Workshop, Aug. 1997. Available from http: //www-suif. stanford. edu/suifconf/suifconf2/.
    • (1997) Proceedings of the Second SUIF Compiler Workshop
    • Holloway, G.1    Young, C.2
  • 16
    • 0032099295 scopus 로고    scopus 로고
    • Hardware Compilation: Translating Programs into Circuits
    • June
    • N. Wirth. Hardware Compilation: Translating Programs into Circuits. IEEE Computer, 31(6): 25-31, June 1998.
    • (1998) IEEE Computer , vol.31 , Issue.6 , pp. 25-31
    • Wirth, N.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.