SCOPUS 정보 검색 플랫폼

Microelectronics Reliability

Volumn 51, Issue 5, 2011, Pages 919-924

Cross-cell interference variability aware model of fully planar NAND Flash memory including line edge roughness

(5) Poliakov, Pavel a,b Blomme, Pieter a Corbalan, Miguel Miranda a Houdt, Jan Van a Dehaene, Wim a,b

a IMEC (Belgium)

b UNIVERSITY OF LEUVEN (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVE AREA; ALTERNATIVE APPROACH; CAPACITIVE COUPLINGS; CELL INTERFERENCE; ELECTRICAL BEHAVIORS; FLOATING GATE TRANSISTORS; FLOATING GATES; LINE EDGE ROUGHNESS; NAND FLASH MEMORY; PROBABILISTIC FRAMEWORK; PROCESS TECHNOLOGIES; SIMULATION-BASED; SYSTEM LEVELS; TECHNOLOGICAL LIMITATIONS; VOLTAGE DISTURBANCES;

COUPLINGS; MICROELECTRONICS; MICROPROCESSOR CHIPS; NAND CIRCUITS; ROUGHNESS MEASUREMENT;

FLASH MEMORY;

EID: 79953647812 PISSN: 00262714 EISSN: None Source Type: Journal
DOI: 10.1016/j.microrel.2010.12.010 Document Type: Article

Times cited : (23)

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