Electrical impact of line-edge roughness on sub-45nm node standard cell

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 7275, Issue , 2009, Pages

  Ban, Yongchan ^a   Sundareswaran, Savithri ^b   Panda, Rajendran ^b   Pan, David Z ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^b FREESCALE SEMICONDUCTOR INC   (United States)

Author keywords

Circuit performance; DFM; LER; Line edge roughness; Standard cell; Sub 45nm process

Indexed keywords

CIRCUIT PERFORMANCE; DFM; LER; LINE-EDGE ROUGHNESS; STANDARD CELL; SUB-45NM PROCESS;

ELECTRIC BATTERIES; ELECTRIC NETWORK ANALYSIS; ELECTRON BEAM LITHOGRAPHY; MACHINE DESIGN; MOSFET DEVICES; PHOTORESISTS; STANDARDS; VLSI CIRCUITS;

ROUGHNESS MEASUREMENT;

EID: 66749137797     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.814355     Document Type: Conference Paper

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