Extraction of 3D parasitic capacitances in 90 nm and 22 nm NAND flash memories

Microelectronics Reliability

Volumn 49, Issue 9-11, 2009, Pages 1056-1059

  Postel Pellerin, J ^a   Lalande, F ^a   Canet, P ^a   Bouchakour, R ^a   Jeuland, F ^b   Bertello, B ^b   Villard, B ^b  

^a AIX MARSEILLE UNIVERSITÉ   (France)

^b ATMEL   (France)

Author keywords

[No Author keywords available]

Indexed keywords

FLASH MEMORY; MEMORY ARCHITECTURE; NAND CIRCUITS; NANOTECHNOLOGY;

3D PARASITIC CAPACITANCE; CELL SIZE; FUTURE TECHNOLOGIES; NAND FLASH MEMORY; PARASITIC CAPACITANCE; TCAD SIMULATION; TEST STRUCTURE;

CAPACITANCE;

EID: 69349101932     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2009.06.020     Document Type: Article

References (7)

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