Using data postcompensation and predistortion to tolerate cell-to-cell interference in MLC nand flash memory

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 57, Issue 10, 2010, Pages 2718-2728

  Dong, Guiqiang ^a   Li, Shu ^b   Zhang, Tong ^a  

^a RENSSELAER POLYTECHNIC INSTITUTE   (United States)

^b MARVELL SEMICONDUCTOR INC   (United States)

Author keywords

Cell to cell interference; nand flash memory; postcompensation; predistortion

Indexed keywords

CELLS; COMMERCE; CYTOLOGY; DATA HANDLING; DIGITAL COMMUNICATION SYSTEMS; MEMORY ARCHITECTURE; SIGNAL PROCESSING;

CELL-TO-CELL INTERFERENCES; DATA PROCESSING TECHNIQUES; NAND FLASH MEMORY; POST COMPENSATIONS; PRE-DISTORTION; SIGNAL PROCESSING TECHNIQUE; TECHNOLOGY SCALING; THEORETICAL FRAMEWORK;

FLASH MEMORY;

EID: 77957898678     PISSN: 15498328     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2010.2046966     Document Type: Article

References (32)

1. 2 16 Gb 4-MLC NAND flash memory with 43 nm CMOS technology", in Proc. IEEE ISSCC, 2008, pp. 430-431, 625.
2. 2 32 Gb 3 b/cell NAND flash memory", in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 2009, pp. 242-243.
3. Y. Li, S. Lee, Y. Fong, F. Pan, T.-C. Kuo, J. Park, T. Samaddar, H. T. Nguyen, M. L. Mui, K. Htoo, T. Kamei, M. Higashitani, E. Yero, G. Kwon, P. Kliza, J. Wan, T. Kaneko, H. Maejima, H. Shiga, M. Hamada, N. Fujita, K. Kanebako, E. Tam, A. Koh, I. Lu, C. C.-H. Kuo, T. Pham, J. Huynh, Q. Nguyen, H. Chibvongodze, M. Watanabe, K. Oowada, G. Shah, B. Woo, R. Gao, J. Chan, J. Lan, P. Hong, L. Peng, D. Das, D. Ghosh, V. Kalluru, S. Kulkarni, R.-A. Cernea, S. Huynh, D. Pantelakis, C.-M. Wang, and K. Quader, "A 16 Gb 3-bit per cell (X3) NAND flash memory on 56 nm technology with 8 MB/s write rate", IEEE J. Solid-State Circuits, vol. 44, no. 1, pp. 195-207, Jan. 2009.
4. S.-H. Chang, S.-K. Lee, S.-J. Park, M.-J. Jung, J.-C. Han, I.-S. Wang, K.-H. Lim, J.-H. Lee, J.-H. Kim, W.-K. Kang, T.-K. Kang, H.-S. Byun, Y.-J. Noh, L.-H. Kwon, B.-K. Koo, M. Cho, J.-S. Yang, and Y.-H. Koh, "A 48 nm 32 Gb 8-level NAND flash memory with 5.5 MB/s program throughput", in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 2009, pp. 240-241.
5. N. Shibata, H. Maejima, K. Isobe, K. Iwasa, M. Nakagawa, M. Fujiu, T. Shimizu, M. Honma, S. Hoshi, T. Kawaai, K. Kanebako, S. Yoshikawa, H. Tabata, A. Inoue, T. Takahashi, T. Shano, Y. Komatsu, K. Nagaba, M. Kosakai, N. Motohashi, K. Kanazawa, K. Imamiya, H. Nakai, M. Lasser, M. Murin, A. Meir, A. Eyal, and M. Shlick, "A 70 nm 16 Gb 16-level-cell NAND flash memory", IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 929-937, Apr. 2008. (Pubitemid 351464086)
6. C. Trinh, N. Shibata, T. Nakano, M. Ogawa, J. Sato, Y. Takeyama, K. Isobe, B. Le, F. Moogat, N. Mokhlesi, K. Kozakai, P. Hong, T. Kamei, K. Iwasa, J. Nakai, T. Shimizu, M. Honma, S. Sakai, T. Kawaai, S. Hoshi, J. Yuh, C. Hsu, T. Tseng, J. Li, J. Hu, M. Liu, S. Khalid, J. Chen, M. Watanabe, H. Lin, J. Yang, K. McKay, K. Nguyen, T. Pham, Y. Matsuda, K. Nakamura, K. Kanebako, S. Yoshikawa, W. Igarashi, A. Inoue, T. Takahashi, Y. Komatsu, C. Suzuki, K. Kanazawa, M. Higashitani, S. Lee, T. Murai, J. Lan, S. Huynh, M. Murin, M. Shlick, M. Lasser, R. Cernea, M. Mofidi, K. Schuegraf, and K. Quader, "A 5.6 MB/s 64 Gb 4 b/Cell NAND flash memory in 43 nm CMOS", in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 2009, pp. 246-247.
7. N. Mielke, T. Marquart, N. Wu, J. Kessenich, H. Belgal, E. Schares, F. Trivedi, E. Goodness, and L. R. Nevill, "Bit error rate in NAND flash memories", in Proc. IEEE Int. Rel. Phys. Symp., 2008, pp. 9-19.
8. K. Kim, "Future memory technology: Challenges and opportunities", in Proc. Int. Symp. VLSI Technol, Syst. Appl., Apr. 2008, pp. 5-9.
9. K. Prall, "Scaling non-volatile memory below 30 nm", in Proc. IEEE 2nd Non-Volatile Semiconductor Memory Workshop, Aug. 2007, pp. 5-10.
10. H. Liu, S. Groothuis, C. Mouli, J. Li, K. Parat, and T. Krishnamohan, "3D simulation study of cell-cell interference in advanced NAND flash memory", in Proc. IEEE Workshop Microelectron. Electron Devices, Apr. 2009, pp. 1-3.
11. E. A. Lee and D. G. Messerschmidt, Digital Communication. Norwell, MA: Kluwer, 1994.
12. J. Chen, Y. Gu, and K. K. Parhi, "Novel FEXT cancellation and equalization for high speed ethernet transmission", IEEE Trans. Circuits Syst. I Reg. Papers, vol. 56, no. 6, pp. 1272-1285, Jun. 2009.
13. T. M. Hollis, D. J. Comer, and D. T. Comer, "Mitigating ISI through self-calibrating continuous-time equalization", IEEE Trans. Circuits Syst. I Reg. Papers, vol. 53, no. 10, pp. 2234-2245, Oct. 2006. (Pubitemid 44637791)
14. S. Hoyos, J. A. Garcia, and G. R. Arce, "Mxed-signal equalization architectures for printed circuit board channels", IEEE Trans. Circuits Syst. I Reg. Papers, vol. 51, no. 2, pp. 264-274, Feb. 2004. (Pubitemid 34711149)
15. Y. H. Chung and S. M. Phoong, "Unitary precoders for ST-OFDM systems using alamouti STBC", IEEE Trans. Circuits Syst. I Reg. Papers, vol. 55, no. 9, pp. 2860-2869, Oct. 2008.
16. Y. Li and Y. Fong, "Compensating for coupling based on sensing a neighbor using coupling", USA Patent 7 522 454, Apr. 2009.
17. K.-D. Suh, B.-H. Suh, Y.-H. Lim, J.-K. Kim, Y.-J. Choi, Y.-N. Koh, S.-S. Lee, S.-C. Kwon, B.-S. Choi, J.-S. Yum, J.-H. Choi, J.-R. Kim, and H.-K. Lim, "A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme", IEEE J. Solid-State Circuits, vol. 30, no. 11, pp. 1149-1156, Nov. 1995.
18. R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti, "Introduction to flash memory", Proc. IEEE, vol. 91, no. 4, pp. 489-502, Apr. 2003. (Pubitemid 43773305)
19. 2 8-Gb multi-level NAND flash memory with 10-mb/s program throughput", IEEE J. Solid-State Circuits, vol. 42, no. 1, pp. 219-232, Jan. 2007. (Pubitemid 46103886)
20. K.-T. Park, M. Kang, D. Kim, S.-W Hwang, B. Y. Choi, Y.-T. Lee, C. Kim, and K. Kim, "A zeroing cell-to-cell interference page architecture with temporary LSB storing and parallel MSB program scheme for MLC NAND flash memories", IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 919-928, Apr. 2008. (Pubitemid 351464085)
21. Y. Li, S. Lee, Y. Fong, F. Pan, T.-C. Kuo, J. Park, T. Samaddar, H. Nguyen, M. Mui, K. Htoo, T. Kamei, M. Higashitani, E. Yero, G. Kwon, P. Kliza, J. Wan, T. Kaneko, H. Maejima, H. Shiga, M. Hamada, N. Fujita, K. Kanebako, E. Tarn, A. Koh, I. Lu, C. Kuo, T. Pham, J. Huynh, Q. Nguyen, H. Chibvongodze, M. Watanabe, K. Oowada, G. Shah, B. Woo, R. Gao, J. Chan, J. Lan, P. Hong, L. Peng, D. Das, D. Ghosh, V. Kalluru, S. Kulkarni, R. Cernea, S. Huynh, D. Pantelakis, C.-M. Wang, and K. Quader, "A 16 Gb 3 b/Cell NAND flash memory in 56 nm with 8 MB/s write rate", in Proc. IEEE ISSCC, Feb. 2008, pp. 506-632.
22. R.-A. Cernea, L. Pham, F. Moogat, S. Chan, B. Le, Y. Li, S. Tsao, T.-Y. Tseng, K. Nguyen, J. Li, J. Hu, J. H. Yuh, C. Hsu, F. Zhang, T. Kamei, H. Nasu, P. Kliza, K. Htoo, J. Lutze, Y. Dong, M. Higashitani, J. Yang, H.-S. Lin, V. Sakhamuri, A. Li, F. Pan, S. Yadala, S. Taigor, K. Pradhan, J. Lan, J. Chan, T. Abe, Y. Fukuda, H. Mukai, K. Kawakami, C. Liang, T. Ip, S.-F. Chang, J. Lakshmipathi, S. Huynh, D. Pantelakis, M. Mofidi, and K. Quader, "A 34 MB/s MLC write throughput 16 Gb NAND with all bit line architecture on 56 nm technology", IEEE J. Solid-State Circuits, vol. 44, no. 1, pp. 186-194, Jan. 2009.
23. J.-D. Lee, S.-H. Hur, and J.-D. Choi, "Effects of floating-gate interference on NAND flash memory cell operation", IEEE Electron. Device Lett., vol. 23, no. 5, pp. 264-266, May 2002.
24. K. Takeuchi, T. Tanaka, and H. Nakamura, "A double-level-Vth select gate array architecture for multilevel NAND flash memories", IEEE J. Solid-State Circuits, vol. 31, no. 4, pp. 602-609, Apr. 1996. (Pubitemid 126606522)
25. N. Shibata, H. Maejima, K. Isobe, K. Iwasa, M. Nakagawa, M. Fujiu, T. Shimizu, M. Honma, S. Hoshi, T. Kawaai, K. Kanebako, S. Yoshikawa, H. Tabata, A. Inoue, T. Takahashi, T. Shano, Y. Komatsu, K. Nagaba, M. Kosakai, N. Motohashi, K. Kanazawa, K. Imamiya, and H. Nakai, "A 70 nm 16 Gb 16-level-cell NAND flash memory", in Proc. IEEE Symp. VLSI Circuits, 2007, pp. 190-191. (Pubitemid 351464086)
26. G. Matamis, T. Pham, H. Chien, and H. Fang", Bitline direction shielding to avoid cross coupling between adjacent cells for NAND flash memory", USA Patent 7221 008, May 22, 2007.
27. J. W. Lutze and N. Mokhlesi", Shield plate for limiting cross coupling between floating gates", USA Patent 7355 237, Apr. 2008.
28. H. Chien and Y. Fong", Deep Wordline Trench to Shield Cross Coupling Between Adjacent Cells for Scaled NAND", USA Patent 7 170 786, Jan. 30, 2007.
29. T. M. Cover and J. A. Thomas, Elements of Information Theory. Hoboken, NJ: Wiley, 1991.
30. R. J. McEliece, The Theory of Information and Coding. Cambridge, U. K.: Cambridge Univ. Press, 2002.
31. J. M. May, Parallel I/O for High Performance Computing. San Mateo, CA: Morgan Kaufmann, 2000.
32. E. Gal and S. Toledo, "Algorithms and data structures for flash memories", ACM Comput. Surv., vol. 37, no. 2, pp. 138-163, Jun. 2005. (Pubitemid 41527575)