Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors

IEEE Journal of Solid-State Circuits

Volumn 38, Issue 5, 2003, Pages 826-829

  Tschanz, James W ^a   Narendra, Siva ^a   Nair, Raj ^a   De, Vivek ^a  

^a Microprocessor Research Laboratories   (United States)

Author keywords

Body bias; CMOS digital integrated circuits; Forward bias; Low power circuits; Microprocessors; Parameter variation; Substrate bias; Within die variation

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; ELECTRIC POWER SUPPLIES TO APPARATUS; INTEGRATED CIRCUIT MANUFACTURE;

ADAPTIVE SUPPLY VOLTAGE; BODY BIAS; PARAMETER VARIATIONS;

MICROPROCESSOR CHIPS;

EID: 0038528639     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2003.810053     Document Type: Article

References (5)

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3. J. Tschanz, J. Kao, S. Narendra, R. Nair, D. Antoniadis, A. Chandrakasan, and V. De, "Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2002, pp. 422-423.
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