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Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2008, Pages 18-23

Characterization of stacked die using die-to-wafer integration for high yield and throughput

(13) Sakuma, K a Andry, P S b Tsang, C K b Sueoka, K a Oyama, Y c Patel, C b Dang, B b Wright, S L b Webb, B C b Sprogis, E d Polastre, R b Horton, R b Knickerbocker, J U b

a IBM RESEARCH TOKYO (Japan)

b IBM T J WATSON RESEARCH CENTER (United States)

c IBM JAPAN LTD (Japan)

d IBM (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHAINS; COMPUTER NETWORKS; COPPER; INTEGRATION; SEMICONDUCTING SILICON COMPOUNDS; SILICON; SILICON WAFERS; TECHNOLOGY; THREE DIMENSIONAL; THROUGHPUT;

ELECTRONIC COMPONENTS; HIGH YIELD; WAFER INTEGRATION TECHNOLOGY;

WAFER BONDING;

EID: 51349143727 PISSN: 05695503 EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/ECTC.2008.4549944 Document Type: Conference Paper

Times cited : (42)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.