Structural reliability assessment of multi-stack package (MSP) under high temperature storage (HTS) testing condition

Microelectronics Reliability

Volumn 46, Issue 9-11, 2006, Pages 1904-1909

  Yang, S Y ^a   Lee, W J ^a   Jeong, S H ^a   Lee, S J ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC WIRE; FINITE ELEMENT METHOD; GOLD; HIGH TEMPERATURE TESTING; INTERFEROMETRY; MOIRE FRINGES; PHOTOSENSITIVITY; SOLDERING ALLOYS;

GOLD WIRES; HIGH TEMPERATURE STORAGE (HTS); KIRKENDALL VOID; MULTI STACK PACKAGE (MSP);

ELECTRONICS PACKAGING;

EID: 33748084380     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2006.07.089     Document Type: Article

References (6)

1. Krishnan S et al. Semiconductor Thermal Measurement and Management Symposium. Twentieth Annual IEEE9-11. 2004. p 64.
2. Kian T.Y., et al. EPTC 10-12 (2003) 767
3. th International, 16-18 July. 2003. p 261.
4. Yeh C.P., Ume I.C., Fulton R.E., Wyatt K.W., and Stafford J.W. Correlation of Analytical and Experimental Approaches to Determine Thermally Induced PWB Warpage. IEEE Trans on Components, Hybrids, and Manufacturing Technology 16 (1993) 986-995
5. Yang S.Y., Jeon Y.D., Lee S.B., and Paik K.W. Solder reflow process induced residual warpage measurement and its influence on reliability of flip chip electronic packages. Microelec Reliab 46 (2006) 512-522
6. Post D., Han B., and Ifju P. High sensitivity moire (1994), Springer-Verlag, New York p 118