High density assembly technology using stacking method

IEEE 9th VLSI Packaging Workshop in Japan, VPWJ 2008

Volumn , Issue , 2008, Pages 149-152

  Maebashi, Takanori ^a   Nakamura, Natsuo ^a   Sacho, Yutaka ^a   Nakayama, Shigeto ^a   Hashimoto, Eiri ^a   Toyoda, Shinjiro ^a   Miyakawa, Nobuaki ^a  

^a HONDA RESEARCH INSTITUTE JAPAN CO LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CONNECTORS; MICROPROCESSOR CHIPS; SEMICONDUCTING SILICON COMPOUNDS; SILICON WAFERS; TECHNOLOGY;

3-DIMENSIONAL; ASSEMBLY TECHNOLOGIES; CMOS TECHNOLOGIES; ELECTRICAL CONNECTIONS; HIGH DENSITIES; INTERCONNECTION METHODS; INTERCONNECTION RESISTANCES; MICRO BUMPS; PROTOTYPE DEVICES; SIDE PROCESS; STACKING METHODS; STACKING PROCESS; THROUGH-SILICON-VIA; WAFER STACKING; WAFER STACKING TECHNOLOGIES; WAFER THINNING;

CHIP SCALE PACKAGES;

EID: 63049114565     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VPWJ.2008.4762238     Document Type: Conference Paper

References (6)

1. Matsumoto, T., Kudoh, Y., Tahara, M., Yu, K. H., Miyakawa, N., Itani, H., Ichikizaki, T., Fujiwara, A., Tsukamoto, H., and Koyanagi, M., "Three dimensional integration technology based on wafer bonding technique using micro-bumps," Proc. Int. Conf. Solid State Devices and Mater, 1995, pp. 1073-1074.
2. Matsumoto, T., Satoh, M., Sakuma, K., Kurino, H., Miyakawa, N., Itani, H., and Koyanagi, M., "New Three-Dimensional Wafer Bonding Technology Using Adhesive Injection Method," Proc. Int. Conf. Solid State Devices and Mater, 1997, pp. 460-461.
3. Koyanagi, M., Kurino, H., Lee, K. W., Sakuma, K., Miyakawa, N., and Itani, H., "Future system-on-silicon LSI chips," IEEE Micro, vol. 18, no. 4 (1998), pp. 17-22.
4. Iwata, A., Sasaki, M., Kikkawa, T., Kameda, S., Ando, H., Kimoto, K., Arizono, D., H., "A 3D Integration Scheme Utilizing Wireless Interconnections for Implementing Hyper Brains," ISSCC Dig. Tech. Papers, 2005, pp. 262-263.
5. Fukushima T., Yamada, Y., Kikuchi, H., and Koyanagi, M., "New Three-Dimensional Integration Technology Using Self-Assembly Technique," IEEE Int'l Electron Devices Meeting Conf. Dig. Tech. Papers, 2005, pp. 359-362.
6. Maebashi, T., Nakamura, N., Nakayama, N., and Miyakawa, N., "New Fabrication Method for Multi-Layer Stacked Devices using Wafer-to-Wafer Stacked Technology based on 8-inch Wafers" Proc The 3th ESSDERC, 2007, pp. 251-254.