TSV process using bottom-up Cu electroplating and its reliability test

Proceedings - 2008 2nd Electronics Systemintegration Technology Conference, ESTC

Volumn , Issue , 2008, Pages 645-650

  Chang, H H ^a   Shih, Y C ^a   Hsu, C K ^a   Hsiao, Z C ^a   Chiang, C W ^a   Chen, Y H ^a   Chiang, K N ^b  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

^b NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ASPECT RATIO; CHEMICAL VAPOR DEPOSITION; COPPER; COPPER PLATING; ELECTROCHEMISTRY; ELECTRONIC EQUIPMENT MANUFACTURE; ELECTRONICS PACKAGING; ELECTROPLATING; PHOTORESISTS; POLYCHLORINATED BIPHENYLS; PRESSURE DROP; RELIABILITY; SEMICONDUCTING SILICON COMPOUNDS; SHEAR STRENGTH; SILICON WAFERS; WAFER BONDING;

AU BUMPS; BONDING CONDITIONS; BONDING PROCESSES; BONDING STRENGTHS; BOTTOM ELECTRODES; BOTTOM-UP; COPPER ELECTROPLATING; CORE TECHNOLOGIES; CU ELECTROPLATING; DC POWER SUPPLIES; DUMMY WAFERS; ELECTROPLATING MACHINES; ETCH MASKS; HIGH ASPECT RATIOS; LASER DRILLINGS; PROCESS NEEDS; PROCESS USING; PULL TESTS; RELIABILITY TESTS; SEED LAYERS; SHOCK RELIABILITIES; STEP COVERAGES; THROUGH-SILICON-VIA; VOID FREE;

GOLD;

EID: 58149093789     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESTC.2008.4684427     Document Type: Conference Paper

References (10)

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