Modelling of the hole mobility in p-channel MOS transistors fabricated on (1 1 0) oriented silicon wafers

Solid-State Electronics

Volumn 54, Issue 4, 2010, Pages 420-426

  Gaubert, Philippe ^a   Teramoto, Akinobu ^a   Ohmi, Tadahiro ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

(1 1 0) orientation; Extraction methods; Hole mobility; Mobility attenuation factor; Scattering mechanisms; Simulation

Indexed keywords

(1 1 0) ORIENTATION; ATTENUATION FACTORS; CONDUCTION PARAMETERS; CONVENTIONAL METHODS; COULOMB SCATTERING; EFFECTIVE MOBILITIES; EXTRACTION METHOD; LOW FIELD MOBILITY; MOS TRANSISTORS; ORIENTED SILICON; P-CHANNEL MOS; SCATTERING MECHANISMS; SI(1 0 0); STATIC CHARACTERISTIC; SURFACE ROUGHNESS SCATTERING;

PHONON SCATTERING; PHONONS; SEMICONDUCTING SILICON; SEMICONDUCTING SILICON COMPOUNDS; SILICON WAFERS; SURFACE ROUGHNESS; TRANSISTOR TRANSISTOR LOGIC CIRCUITS; TRANSISTORS;

HOLE MOBILITY;

EID: 77349110444     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2009.11.004     Document Type: Article

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