High performance Hi-K + metal gate strain enhanced transistors on (110) silicon

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2008, Pages

  Packan, P ^a   Cea, S ^a   Deshpande, H ^a   Ghani, T ^a   Giles, M ^a   Golonzka, O ^a   Hattendorf, M ^a   Kotlyar, R ^a   Kuhn, K ^a   Murthy, A ^a   Ranade, P ^a   Shifren, L ^a   Weber, C ^a   Zawadzki, K ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

45NM NODES; DEVICE PERFORMANCE; DEVICE RELIABILITIES; DRIVE CURRENTS; METAL GATES; NARROW WIDTHS; NEGATIVE IMPACTS; PERFORMANCE IMPACTS; PMOS DEVICES; SHORT-CHANNEL EFFECTS; SILICON SUBSTRATES;

ELECTRON DEVICES;

SUBSTRATES;

EID: 64549089982     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2008.4796614     Document Type: Conference Paper

References (9)

1. T.Ghani et al., IEDM Tech. Dig., p. 1161, (2003).
2. M.Yang et al., IEDM Tech. Dig., p.453, (2003).
3. T. Mizuno et al., IEEE Trans. Elec. Dev, 52, p.367 (2005).
4. H.Harris et al., IEDM Tech. Dig., p. 57, (2007).
5. K.Mistry et al., IEDM Tech. Dig., p.247, (2007).
6. C.Auth et al., Symp. VLSI Dig., p 128, (2008).
7. J.Luttinger and M.Kohn, Phys. Rev., 97, p. 869, (1955).
8. M. Fischetti, IEEE Trans. Elec. Dev. 38, p.634, (1991).
9. R. Kotlyar et al, J. Comp. Elec. 7, p. 95 (2008).