Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits

Proceedings - Design Automation Conference

Volumn , Issue , 2002, Pages 498-503

  Perrott, Michael H ^a  

^a Massachusetts Institute of Technology Cambridge   (United States)

Author keywords

Delta; DLL; Fractional N; Frequency; PLL; Sigma; Synthesizer

Indexed keywords

COMPUTER SIMULATION; MODULATORS; PHASE LOCKED LOOPS; SIMULATORS;

DELAY LOCKED LOOPS (DLL) CIRCUITS;

FREQUENCY SYNTHESIZERS;

EID: 0036053142     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/dac.2002.1012676     Document Type: Conference Paper

References (13)

1. Nonlinear behavioral modeling and phase noise evaluation in phase locked loops
2. Behavioral simulation techniques for phase/delay-locked systems
3. A general theory of phase noise in electrical oscillators
4. The PLL dead zone and how to avoid it
5. Behavioral modeling and simulation of phase-locked loops for RF front ends
6. A 27 mW CMOS fractional-N synthesizer using digital compensation for 2.5 Mb/s GFSK modulation
7. Delta-sigma modulation in fractional-N frequency synthesis
8. SPICE-compatible behavioral phase-space simulation techniques for phase-locked systems