A 130 mW 100 MS/s pipelined ADC With 69 dB SNDR enabled by digital harmonic distortion correction

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 12, 2009, Pages 3314-3328

  Panigada, Andrea ^a   Galton, Ian ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

ADC; Calibration; Digital; Mixed signal

Indexed keywords

90NM CMOS; AMPLIFIER GAIN; CAPACITOR MISMATCH; DIGITAL BACKGROUND CALIBRATION; FULLY INTEGRATED; LOW VOLTAGE OPERATION; MIXED SIGNAL; NOISE CANCELLATION; NON-LINEARITY; PIPELINED ADCS; POWER DISSIPATION; POWER SUPPLY;

ANALOG TO DIGITAL CONVERSION; CALIBRATION; DIGITAL INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; ERROR CORRECTION; HARMONIC DISTORTION;

MULTICARRIER MODULATION;

EID: 72949087592     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2032637     Document Type: Conference Paper

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