A 16-bit 65-MS/s 3.3-V pipeline ADC core in SiGe BiCMOS with 78-dB SNR and 180-fs jitter

IEEE Journal of Solid-State Circuits

Volumn 40, Issue 6, 2005, Pages 1225-1237

  Zanchi, Alfio ^a   Tsay, Frank ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

Analog to digital converter (ADC); Integral non linearity (INL); Jitter; Pipelined architecture; Silicon germanium BiCMOS; SPICE simulation techniques; Switched capacitor circuits

Indexed keywords

ANALOG TO DIGITAL CONVERSION; BIPOLAR INTEGRATED CIRCUITS; CAPACITORS; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; JITTER; SIGNAL TO NOISE RATIO;

INTEGRAL NONLINEARITY (INL); PIPELINED ARCHITECTURE; SILICON-GERMANIUM BICMOS; SPICE SIMULATION TECHNIQUES; SWITCHED-CAPACITOR CIRCUITS;

CMOS INTEGRATED CIRCUITS;

EID: 20444496586     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2005.848020     Document Type: Article

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