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Volumn , Issue CIRCUITS SYMP., 2004, Pages 152-155

A CMOS 64MSps 20mA 0.85mm2 baseband I/Q modulator performing 13 bits over 2MHz bandwidth

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; BANDWIDTH; CLIENT SERVER COMPUTER SYSTEMS; ELECTRIC GENERATORS; ELECTRIC POTENTIAL; ENERGY DISSIPATION; PULSE TIME MODULATION; VOLTAGE MEASUREMENT; WHITE NOISE;

EID: 4544288999     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (1)

References (9)
  • 1
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    • May
    • W. Khalil et al., "A Highly Integrated Analog Front-End for 3G" IEEE Journal of Solid-State Circuits, Vol.38, No.5, pp. 774-780, May 2003.
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    • Khalil, W.1
  • 2
    • 0037969393 scopus 로고    scopus 로고
    • A 1.2V dual-mode WCDMA/GPRS ΣΔ modulator
    • Feb.
    • A. Dezzani, E. Andre', "A 1.2V Dual-Mode WCDMA/GPRS ΣΔ Modulator" in ISSCC Digest Tech. Papers, pp. 58-59, Feb. 2003.
    • (2003) ISSCC Digest Tech. Papers , pp. 58-59
    • Dezzani, A.1    Andre', E.2
  • 3
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    • A comparison of modulator networks for high-order oversampled ΣΔ analog-to-digital converters
    • Feb.
    • D. B. Ribner, "A Comparison of Modulator Networks for High-Order Oversampled ΣΔ Analog-to-Digital Converters", IEEE Transaction on Circuits and Systems II, Vol.38, No.2, pp. 145-159, Feb. 1991.
    • (1991) IEEE Transaction on Circuits and Systems II , vol.38 , Issue.2 , pp. 145-159
    • Ribner, D.B.1
  • 4
    • 0034479805 scopus 로고    scopus 로고
    • A 90dB SNR 2.5MHz output-rate ADC using cascaded multibit delta-sigma modulation and 8X oversampling ratio
    • Dec.
    • I. Fujimori, et al., "A 90dB SNR 2.5MHz Output-Rate ADC Using Cascaded Multibit Delta-Sigma Modulation and 8X Oversampling Ratio", IEEE Journal of Solid-State Circuits, vol.35, No. 12, pp. 1820-1827, Dec.2000.
    • (2000) IEEE Journal of Solid-state Circuits , vol.35 , Issue.12 , pp. 1820-1827
    • Fujimori, I.1
  • 5
    • 0036908706 scopus 로고    scopus 로고
    • A 64MHz clock-rate ΣΔ ADC with 88dB SNDR and -105dB IM3 distortion at a 1.5MHz signal frequency
    • Dec.
    • S. K. Gupta, and V. Fong, "A 64MHz Clock-Rate ΣΔ ADC With 88dB SNDR and -105dB IM3 Distortion at a 1.5MHz Signal Frequency", IEEE Journal of Solid-State Circuits, vol.37, No. 12, pp. 1653-1661, Dec.2002.
    • (2002) IEEE Journal of Solid-state Circuits , vol.37 , Issue.12 , pp. 1653-1661
    • Gupta, S.K.1    Fong, V.2
  • 6
    • 0031333312 scopus 로고    scopus 로고
    • A cascaded ΣΔ pipeline A/D converter with 1.25MHz signal bandwidth and 89dB SNR
    • Dec.
    • T. L. Brooks, et al., "A Cascaded ΣΔ Pipeline A/D Converter with 1.25MHz Signal Bandwidth and 89dB SNR", IEEE Journal of Solid-State Circuits, vol.32, No.12, pp. 1896-1906, Dec.1997.
    • (1997) IEEE Journal of Solid-state Circuits , vol.32 , Issue.12 , pp. 1896-1906
    • Brooks, T.L.1
  • 8
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    • "Linearity enhancement of multibit ΣΔ A/D converters" Using data weighted averaging
    • Dec.
    • R. T. Baird and T. S. Fiez, "Linearity Enhancement of Multibit ΣΔ A/D Converters" Using data Weighted Averaging, IEEE Transaction on Circuits and Systems II, vol.42, No.12, pp. 753-762, Dec. 1995.
    • (1995) IEEE Transaction on Circuits and Systems II , vol.42 , Issue.12 , pp. 753-762
    • Baird, R.T.1    Fiez, T.S.2
  • 9
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    • A fully differential sample-and-hold circuit for high-speed applications
    • Oct.
    • G. Nicollini et al., "A Fully Differential Sample-and-Hold Circuit for High-Speed Applications', IEEE JSSC, vol.24, No.5, pp. 1461-1465, Oct. 1989.
    • (1989) IEEE JSSC , vol.24 , Issue.5 , pp. 1461-1465
    • Nicollini, G.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.