Inversion schemes for sublithographic programmable logic arrays

IET Computers and Digital Techniques

Volumn 3, Issue 6, 2009, Pages 625-642

  Gojman, B ^a   Manem, H ^b   Rose, G S ^b   Dehon, A ^c  

^a UNIVERSITY OF PENNSYLVANIA   (United States)

^b POLYTECHNIC UNIVERSITY   (United States)

^c UNIVERSITY OF PENNSYLVANIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DUAL-RAIL LOGIC; INVERSION SCHEME; LOWER ENERGIES; NANOSCALE ARCHITECTURES; NEGATIVE POLARITY; PRODUCT TERM; PROGRAMMABLE LOGIC ARRAY; PROGRAMMABLE LOGIC DEVICE; RAIL SCHEMES; TIMING MODELS; TORONTO;

EVOLUTIONARY ALGORITHMS; LOGIC DEVICES; MODELS;

PROGRAMMABLE LOGIC CONTROLLERS;

EID: 70350728980     PISSN: 17518601     EISSN: None     Source Type: Journal    
DOI: 10.1049/iet-cdt.2008.0128     Document Type: Article

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