Performance-driven mapping for CPLD architectures

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 22, Issue 10, 2003, Pages 1424-1431

  Chen, Deming ^a   Cong, Jason ^a   Ercegovac, Milos ^a   Huang, Zhijun ^a,b  

^a University of California   (United States)

^b SYNOPSYS INC   (United States)

Author keywords

Complex programmable logic device (CPLD) architecture; Technology mapping

Indexed keywords

ALGORITHMS; COMPUTER AIDED SOFTWARE ENGINEERING; GRAPH THEORY; LOGIC DESIGN; LOGIC GATES; PERFORMANCE; TABLE LOOKUP;

COMPLEX PROGRAMMABLE LOGIC DEVICE ARCHITECTURE; PERFORMANCE-DRIVEN PROGRAMMABLE LOGIC ARRAY MAPPING ALGORITHM;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0142118131     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2003.818120     Document Type: Article

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