Debugging of toffoli networks

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2009, Pages 1284-1289

  Wille, Robert ^a   Große, Daniel ^a   Frehse, Stefan ^a   Dueck, Gerhard W ^b   Drechsler, Rolf ^a  

^a UNIVERSITY OF BREMEN   (Germany)

^b UNIVERSITY OF NEW BRUNSWICK   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC GATES; LOGIC SYNTHESIS; QUANTUM COMPUTERS;

BOOLEAN SATISFIABILITY; INTENSIVE RESEARCH; POST-CMOS; PROBLEM-BASED; REVERSIBLE CIRCUITS; REVERSIBLE LOGIC; REVERSIBLE LOGIC SYNTHESIS; SPEED UP;

COMPUTER CIRCUITS;

EID: 70350059427     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2009.5090863     Document Type: Conference Paper

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