메뉴 건너뛰기




Volumn 23, Issue 8, 2004, Pages 1220-1230

Fault testing for reversible circuits

Author keywords

Fault testing; Quantum computation; Reversible circuits

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; INTEGER PROGRAMMING; LINEAR PROGRAMMING; LOGIC GATES; MATHEMATICAL MODELS; POWER ELECTRONICS;

EID: 3843147248     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2004.831576     Document Type: Article
Times cited : (116)

References (24)
  • 1
    • 0019599728 scopus 로고
    • An information theoretic approach to digital fault testing
    • Aug.
    • V. D. Agrawal, "An information theoretic approach to digital fault testing," IEEE Trans. Comput., vol. 30, pp. 582-587, Aug. 1981.
    • (1981) IEEE Trans. Comput. , vol.30 , pp. 582-587
    • Agrawal, V.D.1
  • 2
    • 0015680909 scopus 로고
    • Logical reversibility of computation
    • C. H. Bennett, "Logical reversibility of computation," IBM J. Res. Develop., vol. 17, pp. 525-532, 1973.
    • (1973) IBM J. Res. Develop. , vol.17 , pp. 525-532
    • Bennett, C.H.1
  • 3
    • 0016049204 scopus 로고
    • Sur la recherche de l'inverse d'un automate
    • J. C. Bertrand, N. Giambiasi, and J. J. Mercier, "Sur la recherche de l'inverse d'un automate," RAIRO, pp. 64-87, 1974.
    • (1974) RAIRO , pp. 64-87
    • Bertrand, J.C.1    Giambiasi, N.2    Mercier, J.J.3
  • 4
    • 0016083810 scopus 로고
    • Sur la recherche de l'inverse d'un circuit combinatoire
    • J. C. Bertrand, J. J. Mercier, and N. Giambiasi, "Sur la recherche de l'inverse d'un circuit combinatoire," RAIRO, pp. 21-44, 1974.
    • (1974) RAIRO , pp. 21-44
    • Bertrand, J.C.1    Mercier, J.J.2    Giambiasi, N.3
  • 5
    • 0035823466 scopus 로고    scopus 로고
    • Time and space bounds for reversible simulation
    • H. Buhrman, J. Tromp, and P. Vitányi, "Time and space bounds for reversible simulation," J. Phys. A: Math. Gen., vol. 34, pp. 6821-6830, 2001.
    • (2001) J. Phys. A: Math. Gen. , vol.34 , pp. 6821-6830
    • Buhrman, H.1    Tromp, J.2    Vitányi, P.3
  • 7
    • 0029406001 scopus 로고
    • Test set compaction for combinational circuits
    • Nov.
    • J.-S. Chang and C.-S. Lin, "Test set compaction for combinational circuits," IEEE Trans. Computer-Aided Design, vol. 14, pp. 1370-1378, Nov. 1995.
    • (1995) IEEE Trans. Computer-aided Design , vol.14 , pp. 1370-1378
    • Chang, J.-S.1    Lin, C.-S.2
  • 9
    • 0036900183 scopus 로고    scopus 로고
    • A reversible carry-look-ahead adder using control gates
    • B. Desoete and A. De Vos, "A reversible carry-look-ahead adder using control gates," Integration, VLSI J., vol. 33, pp. 89-104, 2002.
    • (2002) Integration, VLSI J. , vol.33 , pp. 89-104
    • Desoete, B.1    De Vos, A.2
  • 10
    • 0033361470 scopus 로고    scopus 로고
    • On applying set covering models to test set compaction
    • P. F. Flores, H. C. Neto, and J. P. Marques-Silva, "On applying set covering models to test set compaction," in Proc. GLS-VLSI, 1999, pp. 8-11.
    • (1999) Proc. GLS-VLSI , pp. 8-11
    • Flores, P.F.1    Neto, H.C.2    Marques-Silva, J.P.3
  • 13
    • 0018809498 scopus 로고
    • Test generation & dynamic compaction of test
    • P. Goel and B. C. Rosales, "Test generation & dynamic compaction of test," in Dig. Papers Test Conf., 1979, pp. 189-192.
    • (1979) Dig. Papers Test Conf. , pp. 189-192
    • Goel, P.1    Rosales, B.C.2
  • 14
    • 0015203081 scopus 로고
    • On realizations of Boolean functions requiring a minimal or near minimal number of tests
    • Dec.
    • J. P. Hayes, "On realizations of Boolean functions requiring a minimal or near minimal number of tests," IEEE Trans. Comput., vol. 20, pp. 1506-1513, Dec. 1971.
    • (1971) IEEE Trans. Comput. , vol.20 , pp. 1506-1513
    • Hayes, J.P.1
  • 15
    • 0030261541 scopus 로고    scopus 로고
    • An optimal test compression procedure for combinational circuits
    • Oct.
    • D. S. Hochbaum, "An optimal test compression procedure for combinational circuits," IEEE Trans. Computer-Aided Design, vol. 15, pp. 1294-1299, Oct. 1996.
    • (1996) IEEE Trans. Computer-aided Design , vol.15 , pp. 1294-1299
    • Hochbaum, D.S.1
  • 16
    • 3843124538 scopus 로고    scopus 로고
    • Online
    • ILOG CPLEX [Online]. Available: http://www.ilog.com/products/cplex
  • 18
    • 0000328287 scopus 로고
    • Irreversibility and heat generation in the computing process
    • R. Landauer, "Irreversibility and heat generation in the computing process," IBM J. Res. Develop., vol. 3, pp. 183-191, 1961.
    • (1961) IBM J. Res. Develop. , vol.3 , pp. 183-191
    • Landauer, R.1
  • 19
    • 0006972055 scopus 로고    scopus 로고
    • Reversible simulation of irreversible computation
    • M. Li, J. Tromp, and P. Vitányi, "Reversible simulation of irreversible computation," Phys. D, vol. 120, pp. 168-176, 1998.
    • (1998) Phys. D , vol.120 , pp. 168-176
    • Li, M.1    Tromp, J.2    Vitányi, P.3
  • 20
    • 0003581572 scopus 로고    scopus 로고
    • On the generation of test patterns for combinational circuits
    • Dept. Elect. Eng
    • H. K. Lee and D. S. Ha, "On the Generation of Test Patterns for Combinational Circuits," Dept. Elect. Eng., Virginia Polytech. Inst. State Univ., Tech. Rep. 12_93.
    • Virginia Polytech. Inst. State Univ., Tech. Rep. , vol.12 , Issue.93
    • Lee, H.K.1    Ha, D.S.2
  • 23
    • 84978092325 scopus 로고
    • Reversible computing
    • J. W. de Bakker and J. van Leeuwen, Eds. New York: Springer-Verlag, Lecture Notes in Computer Science
    • T. Toffoli, "Reversible computing," in Automata, Languages and Programming, 7th Colloquium, J. W. de Bakker and J. van Leeuwen, Eds. New York: Springer-Verlag, 1980, Lecture Notes in Computer Science, pp. 632-644.
    • (1980) Automata, Languages and Programming, 7th Colloquium , pp. 632-644
    • Toffoli, T.1
  • 24
    • 3142722173 scopus 로고    scopus 로고
    • Limits to binary logic switch scaling - A Gedanken model
    • Nov.
    • V. V. Zhirnov, R. K. Calvin, III, J. A. Hutchby, and G. I. Bourianoff, "Limits to binary logic switch scaling - A Gedanken model," Proc. IEEE, vol. 91, pp. 1934-1939, Nov. 2003.
    • (2003) Proc. IEEE , vol.91 , pp. 1934-1939
    • Zhirnov, V.V.1    Calvin III, R.K.2    Hutchby, J.A.3    Bourianoff, G.I.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.