Reversible logic Synthesis with Output Permutation

Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems

Volumn , Issue , 2009, Pages 189-194

  Wille, Robert ^a   Große, Daniel ^a   Dueck, Gerhard W ^b   Drechsler, Rolf ^a  

^a UNIVERSITY OF BREMEN   (Germany)

^b UNIVERSITY OF NEW BRUNSWICK   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

HEURISTIC ALGORITHMS; HEURISTIC METHODS; INTEGRATED CIRCUITS; LOGIC GATES; SPECIFICATIONS;

CIRCUIT REALIZATIONS; OUTPUT FUNCTIONS; PERMUTATION VECTORS; RESEARCH AREAS; REVERSIBLE LOGIC; SYNTHESIS ALGORITHMS; SYNTHESIS PROCESS; TRUTH TABLES;

EMBEDDED SYSTEMS;

EID: 62949164659     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSI.Design.2009.40     Document Type: Conference Paper

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