Test generation and fault localization for quantum circuits

Proceedings of The International Symposium on Multiple-Valued Logic

Volumn , Issue , 2005, Pages 62-68

  Perkowski, Marek ^a   Biamonte, Jacob ^a   Lukac, Martin ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC FAULT LOCATION; LOGIC CIRCUITS; MEASUREMENT THEORY; PROBABILISTIC LOGICS; QUANTUM THEORY;

FAULT LOCALIZATION; QUANTUM CIRCUITS; QUANTUM COMPUTING; TEST GENERATION;

ELECTRIC FAULT CURRENTS;

EID: 24644492246     PISSN: 0195623X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (29)

1. Buller, Quantrix: Toward Automated Synthesis of Quantum Cascades, Technical Report TR-HIS-00-*, ATR Human Information Processing Laboratories, Kyoto, 2003. 03.15.
2. H.F. Chau, Correcting quantum errors in higher spin systems. Physical Review A, Vol. 55, R839-R841, 1997.
3. E. Curtis, and M. Perkowski, Minimization of Ternary Reversible Logic Cascades using a Universal Subset of Generalized Ternary Gates, submitted to International Journal on Multiple-Valued Logic and Soft Computing, Svetlana Yanushkevich, editor
4. http://www.dhushara.com/book/quantcos/qcompu/qc2/qc2.htm
5. http://www.themilkyway.com/quantum/FinalReport/QuantumGates.html
6. M. H. A. Khan and M. Perkowski, Genetic Algorithms Based Synthesis of Multi-Output Ternary Functions Using Quantum Cascade of Generalized Ternary Gates, submitted to special issue of International Journal on Multiple-Valued Logic and Soft Computing, Tatjana Kalganova, editor.
7. Z. Kohavi, Switching and Finite Automata Theory, Mc Graw-Hill, 1978.
8. th International Workshop on Boolean Problems, Freiberg University of Mining and Technology, Germany, September 23-24, 2004.
9. A. Muthukrishnan and C. R. Stroud Jr., "Multivalued Logic Gates for Quantum Computation," Physical Review A, Vol. 62, pp. 052309.1-8, 2000.
10. M. Nielsen, and I. Chuang, Quantum Computation and Quantum Information, Cambridge University Press, 2000.
11. K.N. Patel, J.P. Hayes and I. Markov, "Fault testing for reversible circuits," Proc. VLSI Test Symp. (VTS 03), Napa, CA, pp. 410-416, April 2003.
12. B. Patterson, http:www.cs.iastate.edu/~patterbi/cs/quantum.fp/FinalPaper. pdf
13. T. Toffoli, "Reversible Computing", in Automata, Languages and Programming (edited by de J. W. Bakker and J. van Leeuwen), Springer Verlag, pp. 632-644, 1980.
14. G.F.Viamontes, M. Rajagopalan, I.L. Markov and J.P. Hayes, Gate-Level Simulation of Quantum Circuits, quant-ph/0208003.
15. G. F. Viamontes, I. L. Markov and J. P. Hayes, "Improving Gate-Level Simulation of Quantum Circuits" (quant-ph/0309060'). to appear in Quantum Information Processing, 2004.
16. S. Aligala, Simulation and Test generation for ternary quantum circuits with visualization, report, Fall 2004.
17. S. Aligala, S. Ratakonda, K. Narayan, K. Nagarayan, M. Lukac, J. Biamonte and M. Perkowski, Deterministic and Probabilistic Test Generation for Binary and Ternary Quantum Circuits, Proc. ULSI 2004.
18. J. Biamonte, and M. Perkowski, Quantum Fault Detection, submitted, 2004.
19. J. P. Hayes and I. Markov, Principle Investigators, Quantum Approaches to Logic Circuit Synthesis and Testting,http://vlsicad.eecs.umich.edu/Quantum/ summary.html
20. W.N.N. Hung, X. Song, G. Yang, J. Yang, and M. Perkowski, "Quantum Logic Synthesis by Symbolic Reachability Analysis". Proc. 41 DAC, San Diego, California, June 2004.
21. M. Lukac, M. Perkowski, H. Goi, M. Pivtoraiko, C.H. Yu, K. Chung, H. Jee, B-G. Kim, and Y-D. Kim, Evolutionary approach to Quantum and Reversible Circuits synthesis, Artificial Intelligence Review, 20, pp 361-417, 2003. Kluwer Academic Publishers.
22. A. Muthukrishnan, and C. R. Stroud, Jr., Multivalued logic gates for quantum computation, Physical Review A, Vol. 62, No. 5, Nov. 2000, 052309/1-8.
23. M. Perkowski, A. Al-Rabadi, and P. Kerntopf, Multiple-Valued Quantum Logic Synthesis, Proc. 2002 Intern. Symp. on New Paradigm VLSI Computing, Sendai, Japan, December 12-14, 2002, pp. 41-47.
24. K. Ramasamy, R. Tagare, E. Perkins, and M. Perkowski, Fault Localization in Reversible Circuits is Easier than for Classical Circuits. Proc. IWLS 2004.
25. G.F. Viamontes, I. L. Markov and J. P. Hayes, Graph-based simulation of quantum computation in the density matrix representation, arXiv:quant-ph/ 0403114V2, 16 Mar 2004.
26. J. Biamonte, and M. Perkowski, Principles of Quantum Fault Detection, to appear in McNair research Journal, 2004.
27. J. Biamonte, and M. Perkowski, Testing a Quantum Computer, KIAS-KAIST 2004 Workshop on Quantum Information Science. KIAS International Conference Hall, Seoul, Korea, August 29-31th, 2004. Quantum Phys, abstract, quant-ph/0409023.
28. M. Perkowski and S. Aligala, Two Models of Test Generation for Ternary and Quaternary Quantum Circuits. Report, 2004.
29. J.P. Hayes, I. Polian and B. Becker, Testing for Missing-Gate Faults in Reversible Circuits, preprint from authors.