Partially redundant logic detection using symbolic equivalence checking in reversible and irreversible logic circuits

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2008, Pages 1378-1381

  Feinstein, David Y ^a   Thornton, Mitchell A ^a   Miller, D Michael ^b  

^a Southern Methodist University   (United States)

^b UNIVERSITY OF VICTORIA   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

INDUSTRIAL ENGINEERING; NETWORKS (CIRCUITS); QUANTUM THEORY; SWITCHING CIRCUITS; SWITCHING THEORY; TESTING;

AND GATES; BENCHMARK CIRCUITS; BIJECTIVE FUNCTIONS; EQUIVALENCE CHECKER; EQUIVALENCE CHECKING; FAULT COVERAGE; GATE REPLACEMENT; IN-LINE; MAXIMAL INFORMATION; QUANTUM LOGIC; REVERSIBLE CIRCUITS; SINGLE GATE;

LOGIC CIRCUITS;

EID: 49749152033     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2008.4484932     Document Type: Conference Paper

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