Post-verification debugging of hierarchical designs

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn 2005, Issue , 2005, Pages 871-876

  Ali, Moayad Fahim ^a   Safarpour, Sean ^a   Veneris, Andreas ^a   Abadir, Magdy S ^b   Drechsler, Rolf ^c  

^a UNIVERSITY OF TORONTO   (Canada)

^b FREESCALE SEMICONDUCTOR INC   (United States)

^c UNIVERSITY OF BREMEN   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; COMPUTATIONAL COMPLEXITY; COMPUTER AIDED DESIGN; COMPUTER SELECTION AND EVALUATION; ERROR DETECTION; PROBLEM SOLVING; PROGRAM DEBUGGING;

HIERARCHICAL DESIGNS; POST VERIFICATION; QUANTIFIED BOOLEAN FORMULA SATISFIABILITY; VLSI DESIGNS;

HIERARCHICAL SYSTEMS;

EID: 33751398970     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2005.1560184     Document Type: Conference Paper

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