Post-silicon bug localization in processors using instruction footprint recording and analysis (IFRA)

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 28, Issue 10, 2009, Pages 1545-1558

  Park, Sung Boem ^a   Hong, Ted ^a   Mitra, Subhasish ^b  

^a Stanford University   (United States)

^b STANFORD UNIVERSITY   (United States)

Author keywords

Circuit marginality; Design for debug; Electrical bug; Post silicon validation; Silicon debug.

Indexed keywords

CHIP AREAS; CIRCUIT MARGINALITY; DESIGN BLOCKS; ELECTRICAL BUG; NORMAL OPERATIONS; OFFLINE; ON CHIPS; POST-SILICON; POST-SILICON VALIDATION; PROGRAM ANALYSIS; SELF-CONSISTENCY; SILICON DEBUG.; SIMULATION RESULT; SUPERSCALAR PROCESSOR; SYSTEM FAILURES; SYSTEM LEVEL SIMULATION; SYSTEM LEVELS; SYSTEM VALIDATION; TEST PROGRAM; TRADITIONAL TECHNIQUES;

PROGRAM PROCESSORS; SYSTEMS ENGINEERING;

QUALITY ASSURANCE;

EID: 70349732867     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2009.2030595     Document Type: Article

References (36)

1. M. Abramovici, P. Bradley, K. Dwarakanath, P. Levin, G. Memmi, and D. Miller, "A reconfigurable design-for-debug infrastructure for SoCs," in Proc. Des. Autom. Conf., Jul. 2006, pp. 7-12.
2. H. Ando, Y. Yoshida, A. Inoue, I. Sugiyama, T. Asakawa, K. Morita, T. Muta, T. Motokurumada, S. Okada, H. Yamashita, Y. Satsukawa, A. Konmoto, R. Yamashita, and H. Sugiyama, "A 1.3-GHz fifth- generation SPARC64 microprocessor," IEEE J. Solid-State Circuits, vol.38, no.11, pp. 1896-1905, Nov. 2003.
3. A. Agarwal, R. L. Sites, and M. Horowitz, "ATUM: A new technique for capturing address traces using microcode," in Proc. Int. Symp. Comput. Archit., Jun. 1986, pp. 119-127.
4. T. M. Austin, "DIVA: A reliable substrate for deep submicron microarchitecture design," in Proc. Int. Symp. Microarchitecture, Nov. 1999, pp. 196-207.
5. T. Austin, E. Larson, and D. Ernst, "SimpleScalar: An infrastructure for computer system modeling," Computer, vol.35, no.2, pp. 56-67, Feb. 2002.
6. A. A. Bayazit and S. Malik, "Complementary use of runtime validation and model checking," in Proc. Int. Conf. Comput.-Aided Des., 2005, pp. 1052-1059.
7. O. Caty, P. Dahlgren, and I. Bayraktaroglu, "Microprocessor silicon debug based on failure propagation tracing," in Proc. Int. Test Conf., Nov. 2005, pp. 293-302.
8. K. Chang, I. L. Markov, and V. Bertacco, "Automating post-silicon debugging and repair," in Proc. Int. Conf. Comput.-Aided Des., Nov. 2007, pp. 91-98.
9. K. Chen, S. Malik, and P. Patra, "Runtime validation of memory ordering using constraint graph checking," in Proc. Int. Symp. High-Perform. Comput. Archit., Feb. 2008, pp. 415-426.
10. D. W. Clark, "Large-scale hardware simulation: Modeling and verification strategies," in CMU Computer Science: A 25th Anniversary Commemorative, R. F. Rashid, Ed. New York: ACM, 1991, pp. 219-234.
11. F. M. De Paula, M. Gort, A. J. Hu, S. J. E. Wilton, and J. Yang, "BackSpace: Formal analysis for post-silicon debug," in Proc. Formal Methods Comput.-Aided Des., Nov. 2008, pp. 1-10.
12. Alpha 21264 Microprocessor Hardware Reference Manual, Digital Equipment Corporation, Maynard, MA, Jul. 1999.
13. M. D. Goddard and D. S. Christie, "Microcode patching apparatus and method," U.S. Patent 5 796 974, Aug. 18, 1998.
14. J. Gray, "Why do computers stop and what can be done about it," Tandem Comput., Cupertino, CA, Tech. Rep. 85.7, PN 87614, Jun. 1985.
15. M. W. Heath, W. P. Burleson, and I. G. Harris, "Synchro-tokens: Eliminating nondeterminism to enable chip-level test of globally-asynchronous locally-synchronous SoC's," in Proc. Des. Autom. Test Eur., Feb. 2004, pp. 1532-1546.
16. International Technology Roadmap for Semiconductors. 2007 ed.
17. D. Josephson, S. Poehlman, and V. Govan, "Debug methodology for the McKinley processor," in Proc. Int. Test Conf., Oct./Nov. 2001, pp. 451-460.
18. D. Josephson, "The good, the bad, and the ugly ofsilicon debug," in Proc. Des. Autom. Conf., Jul. 2006, pp. 3-6.
19. R. H. Livengood and D. Medeiros, "Design for (physical) debug for silicon microsurgery and probing of flip-chip packaged integrated circuits," in Proc. Int. Test Conf., Sep. 1999, pp. 877-882.
20. D. J. Lu, "Watchdog processors and structural integrity checking," IEEE Trans. Comput., vol.C-31, no.7, pp. 681-685, Jul. 1982.
21. C. MacNamee and D. Heffernan, "Emerging on-chip debugging techniques for real-time embedded systems," Comput. Control Eng. J., vol.11, no.6, pp. 295-303, Dec. 2000.
22. A. Mahmood and E. J. McCluskey, "Concurrent error detection using watchdog processors-A survey," IEEE Trans. Comput., vol.37, no.2, pp. 160-174, Feb. 1988.
23. R. McLaughlin, S. Venkataraman, and C. Lim, "Automated debug of speed path failures using functional tests," in Proc. VLSI Test Symp., May 2009, pp. 91-96.
24. N. Oh, P. P. Shirvani, and E. J. McCluskey, "Control-flow checking by software signatures," IEEE Trans. Rel., vol.51, no.1, pp. 111-122, Mar. 2002.
25. S. Park and S. Mitra, "IFRA: Instruction footprint recording and analysis for post-silicon bug localization in processors," in Proc. Des. Autom. Conf., Jun. 2008, pp. 373-378.
26. P. Patra, "On the cusp of a validation wall," IEEE Des. Test Comput. , vol.24, no.2, pp. 193-196, Mar. 2007.
27. P. N. Sanda, J. W. Kellington, P. Kudva, R. Kalla, R. B. McBeth, J. Ackaret, R. Lockwood, J. Schumann, and C. R. Jones, "Soft-error resilience of the IBM POWER6 processor," IBMJ. Res. Develop., vol.52, no.3, pp. 275-284, May 2008.
28. S. R. Sarangi, B. Greskamp, and J. Torrellas, "CADRE: Cycle-accurate deterministic replay for hardware debugging," in Proc. Int. Conf. Dependable Syst. Netw., Jun. 2006, pp. 301-312.
29. S. R. Sarangi, S. Narayanasamy, B. Carneal, A. Tiwari, B. Calder, and J. Torrellas, "Patching processor design errors with programmable hardware," IEEE Micro, vol.27, no.1, pp. 12-25, Jan./Feb. 2007.
30. J. P. Shen and M. H. Lipasti, Modern Processor Design: Fundamentals of Superscalar Processors. New York: McGraw-Hill, 2005.
31. D. P. Siewiorek and R. S. Swarz, Reliable Computer Systems-Design and Evaluation, 3rd ed. Natick, MA: A.K. Peters, 1998.
32. I. Silas, I. Frumkin, E. Hazan, E. Mor, and G. Zobin, "System-level validation of the Intel Pentium M processor," Intel Technol. J.,vol.7, no.2, pp. 37-43, May 2003.
33. I. Wagner, V. Bertacco, and T. Austin, "Shielding against design flaws with field repairable control logic," in Proc. Des. Autom. Conf., Jul. 2006, pp. 344-347.
34. N. J. Wang, J. Quek, T. M. Rafacz, and S. J. Patel, "Characterizing the effects of transient faults on a high-performance processor pipeline," in Proc. Int. Conf. Dependable Syst. Netw. , Jun./Jul. 2004, pp. 61-70.
35. M. Xu, R. Bodik, and M. D. Hill, "Flight data recorder for enabling full- system multiprocessor deterministic replay," in Proc. Int. Symp. Comput. Archit., May 2003, pp. 122-133.
36. S. Yerramilli, "Addressing post-silicon validation challenge: Leverage validation & test synergy (invited address)," presented at the IEEE Int. Test Conf., Santa Clara, CA, Oct. 25, 2006.