IFRA: Instruction Footprint Recording and Analysis for post-silicon bug localization in processors

Proceedings - Design Automation Conference

Volumn , Issue , 2008, Pages 373-378

  Park, Sung Boem ^a   Mitra, Subhasish ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

Debug; Design for debug; Validation; Verification

Indexed keywords

DEBUG; DESIGN FOR DEBUG; POST-SILICON; VALIDATION; VERIFICATION;

COMPUTER AIDED DESIGN; COMPUTER NETWORKS; DATA STRUCTURES; DIGITAL INTEGRATED CIRCUITS; INDUSTRIAL ENGINEERING; INFORMATION THEORY; PROGRAM PROCESSORS; SILICON;

DESIGN;

EID: 51549119587     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2008.4555846     Document Type: Conference Paper

References (27)

1. Abramovici, et al., "A Reconfigurable Designfor Debug Infrastructure for SOCs", Proc. DAC, 2006.
2. Alpha 21254 Microprocessor Hardware Reference Manual, July 1999.
3. Ando, H., et al., "A 1.3-GHz Fifth-Generation SPARC64 Microprocessor", IEEE JSSC, vol. 38, no. 11, pp. 1896-1905, Nov 2003.
4. Anis, E. and N. Nicolici, "On using lossless compression of debug data in embedded logic analyzers", Proc. Intl. Test Conf., 2007.
5. Austin, T.M., "DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design", Proc. Intl. Symp. on Microarchitecture, 1999.
6. Bayazit, A.A. and S. Malik, "Complementary Use of Runtime Validation and Model Checking", Proc. Intl. Conf. on Computer-aided Design, 2005.
7. Caty, O. P. Dahlgren and I. Bayraktaroglu, "Microprocessor Silicon Debug based on Failure Propagation Tracing", Proc. Intl. Test Conf., 2005.
8. Chen, K., S. Malik, and P. Patra. "Runtime Validation of Memory Ordering Using Constraint Graph Checking". Proc. Intl. Symp. on High-Performance Computer Architecture, 2008.
9. Dahlgren, P., P. Dickinson and I. Parulkar, "Latch Divergence in Microprocessor Failure Analysis", Proc. Intl. Test Conf, 2003.
10. Heath M.W., W.P. Burleson and I.G. Harris, "Synchro-Tokens: Eliminating Nondeterminism to Enable Chip-Level Test of Globally-Asynchronous Locally-Synchronous SoC's", Proc. Conf. on Design, Automation and Test in Europe, ppl 532-1546, 2004. [IVM] http://www.crhc.uiuc.edu/ACS.
11. Josephson, D., "The Good, the Bad, and the Ugly of Silicon Debug", Proc. DAC., 2006.
12. Leon, A.S., B. Langley, and J.L Shin "The UltraSPARC T1 Processor: CMT Reliability", Proc. Custom Integrated Circuits Conf., 2006.
13. Livengood, R. and D. Medeiros, "Design for (physical) Debug for Silicon Microsurgery and Probing of Flipchip Packaged Integrated Circuits", Proc. Intl. Test Conf., 1999.
14. Lu, D.J. "Watchdog Processors and Structural Integrity Checking", IEEE T COMPUT, pp. 681-685, July 1982.
15. MacNamee, C. and D. Heffernan, "Emerging On-chip Debugging Techniques for Real-time Embedded Systems", Computing & Control Engineering Journal, vol. 11, no. 6, pp. 295-303, Dec 2000.
16. Oh, N., S. Mitra and E.J. McCluskey, "ED4I: Error Detection by Diverse Data and Duplicated Instructions", IEEE T COMPUT, vol. 51, no. 2, pp. 180-199, Feb 2002.
17. Patra, P., "On the Cusp of a Validation Wall", IEEE DES TEST COMPUT, vol. 24 no. 2, pp. 193-196, Mar 2007.
18. Park S., and S. Mitra., "IFRA: Instruction Footprint Recording and Analysis for Post-Silicon Bug Localization", Technical Report, Stanford University, 2008, url: http://www.stanford.edu/group/rsg_csl.
19. rd ed., Springer, 2003.
20. Sanda P.N. et al., "Soft-error resilience of the IBM POWER6 processor", IBM Journal of Research and Development, vol. 52, no. 3, 2008
21. Sarangi, S.R., B. Greskamp and J. Torrellas, "CADRE: Cycle-Accurate Deterministic Replay for Hardware Debugging", Intl. Conf. on Dependable Systems and Networks, 2006.
22. Sarangi, S.R., et al., "Patching Processor Design Errors with Programmable Hardware", IEEE MICRO, vol. 27, no. 1, pp. 12-25, Jan 2007.
23. Silas, I., et al., "System-Level Validation of the Intel Pentium M Processor", Intel Technical Journal, May 2003. [simplescalar] www.simplescalar.com.
24. Trong, S.D., et al., "P6 Binary Floating-Point Unit", Proc. Intl. Symp. on Computer Arithmetic, 2007.
25. Wagner, I., V. Bertacco and T. Austin, "Shielding Against Design Flaws with Field Repairable Control Logic", Proc. DAC, 2006.
26. Wang, N.J., et al., "Characterizing the effects of Transient Faults on a High Performance Processor Pipeline". Intl. Conf. on Dependable Systems and Networks, 2004.
27. Yerramilli, S., "Addressing Post-Silicon Validation Challenge: Leverage Validation & Test Synergy (Invited Address)", Intl. Test Conf., 2006.