메뉴 건너뛰기




Volumn 2005, Issue , 2005, Pages 1052-1059

Complementary use of runtime validation and model checking

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; COMPUTATIONAL COMPLEXITY; COMPUTER SELECTION AND EVALUATION; COMPUTER VIRUSES; MATHEMATICAL MODELS; NETWORK PROTOCOLS; PROBLEM SOLVING;

EID: 33751406976     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2005.1560217     Document Type: Conference Paper
Times cited : (37)

References (14)
  • 2
    • 0005440654 scopus 로고    scopus 로고
    • Formal verification in hardware design: A survey
    • C. Kern and M. R. Greenstreet, "Formal verification in hardware design: a survey," ACM Trans. Des. Autom. Electron. Syst., vol. 4, no. 2, pp. 123-193, 1999.
    • (1999) ACM Trans. Des. Autom. Electron. Syst. , vol.4 , Issue.2 , pp. 123-193
    • Kern, C.1    Greenstreet, M.R.2
  • 5
    • 0002584997 scopus 로고
    • Formal verification of the Encore Gigamax cache consistency protocol
    • (sponsored by Information Processing Society, Tokyo, Japan)
    • K.L. McMillan and J. Schwalbe, "Formal verification of the Encore Gigamax cache consistency protocol," in Proceedings of the International Symposium on Shared Memory Multiprocessors, (sponsored by Information Processing Society, Tokyo, Japan), 1991, pp. 242-251.
    • (1991) Proceedings of the International Symposium on Shared Memory Multiprocessors , pp. 242-251
    • McMillan, K.L.1    Schwalbe, J.2
  • 10
    • 0005390122 scopus 로고
    • Processor and memory-based checkpoint and rollback recovery
    • N. S. Bowen and D. K. Pradhan, "Processor and memory-based checkpoint and rollback recovery," Computer, vol. 26, no. 2, pp. 22-31, 1993.
    • (1993) Computer , vol.26 , Issue.2 , pp. 22-31
    • Bowen, N.S.1    Pradhan, D.K.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.