-
2
-
-
0005440654
-
Formal verification in hardware design: A survey
-
C. Kern and M. R. Greenstreet, "Formal verification in hardware design: a survey," ACM Trans. Des. Autom. Electron. Syst., vol. 4, no. 2, pp. 123-193, 1999.
-
(1999)
ACM Trans. Des. Autom. Electron. Syst.
, vol.4
, Issue.2
, pp. 123-193
-
-
Kern, C.1
Greenstreet, M.R.2
-
3
-
-
35048900689
-
20 states and beyond
-
20 states and beyond," Inf. Comput., vol. 98, no. 2, pp. 142-170, 1992.
-
(1992)
Inf. Comput.
, vol.98
, Issue.2
, pp. 142-170
-
-
Burch, J.R.1
Clarke, E.M.2
McMillan, K.L.3
Dill, D.L.4
Hwang, L.J.5
-
4
-
-
84949196273
-
Compositional reasoning in model checking
-
London, UK: Springer-Verlag
-
S. Berezin, S. V. A. Campos, and E. M. Clarke, "Compositional reasoning in model checking," in COMPOS'97: Revised Lectures from the International Symposium on Compositionality: The Significant Difference. London, UK: Springer-Verlag, 1998, pp. 81-102.
-
(1998)
COMPOS'97: Revised Lectures from the International Symposium on Compositionality: The Significant Difference
, pp. 81-102
-
-
Berezin, S.1
Campos, S.V.A.2
Clarke, E.M.3
-
5
-
-
0002584997
-
Formal verification of the Encore Gigamax cache consistency protocol
-
(sponsored by Information Processing Society, Tokyo, Japan)
-
K.L. McMillan and J. Schwalbe, "Formal verification of the Encore Gigamax cache consistency protocol," in Proceedings of the International Symposium on Shared Memory Multiprocessors, (sponsored by Information Processing Society, Tokyo, Japan), 1991, pp. 242-251.
-
(1991)
Proceedings of the International Symposium on Shared Memory Multiprocessors
, pp. 242-251
-
-
McMillan, K.L.1
Schwalbe, J.2
-
6
-
-
0003799504
-
-
New York, NY, USA: Springer-Verlag New York, Inc.
-
Z. Manna and A. Pnueli, The temporal logic of reactive and concurrent systems. New York, NY, USA: Springer-Verlag New York, Inc., 1992.
-
(1992)
The Temporal Logic of Reactive and Concurrent Systems
-
-
Manna, Z.1
Pnueli, A.2
-
7
-
-
33745933222
-
Verification languages
-
R. Zurawski, Ed. CRC Press
-
A. Gupta, A. A. Bayazit, and Y. Mahajan, "Verification languages." in The Industrial Information Technology Handbook, R. Zurawski, Ed. CRC Press, 2005, pp. 1-18.
-
(2005)
The Industrial Information Technology Handbook
, pp. 1-18
-
-
Gupta, A.1
Bayazit, A.A.2
Mahajan, Y.3
-
8
-
-
84937557946
-
NuSMV 2: An OpenSource tool for symbolic model checking
-
A. Cimatti, E. Clarke, E. Giunchiglia, F. Giunchiglia, M. Pistore, M. Roveri, R. Sebastiani, and A. Tacchella, "NuSMV 2: An OpenSource tool for symbolic model checking," Lecture Notes in Computer Science, vol. 2404, pp. 359-364, 2002.
-
(2002)
Lecture Notes in Computer Science
, vol.2404
, pp. 359-364
-
-
Cimatti, A.1
Clarke, E.2
Giunchiglia, E.3
Giunchiglia, F.4
Pistore, M.5
Roveri, M.6
Sebastiani, R.7
Tacchella, A.8
-
10
-
-
0005390122
-
Processor and memory-based checkpoint and rollback recovery
-
N. S. Bowen and D. K. Pradhan, "Processor and memory-based checkpoint and rollback recovery," Computer, vol. 26, no. 2, pp. 22-31, 1993.
-
(1993)
Computer
, vol.26
, Issue.2
, pp. 22-31
-
-
Bowen, N.S.1
Pradhan, D.K.2
-
11
-
-
0033321638
-
DIVA: A reliable substrate for deep submicron microarchitecture design
-
Washington, DC, USA: IEEE Computer Society
-
T. M. Austin, "DIVA: A reliable substrate for deep submicron microarchitecture design," in MICRO 32: Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture. Washington, DC, USA: IEEE Computer Society, 1999, pp. 196-207.
-
(1999)
MICRO 32: Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture
, pp. 196-207
-
-
Austin, T.M.1
-
13
-
-
84944389716
-
Focs: Automatic generation of simulation checkers from formal specifications
-
London, UK: Springer-Verlag
-
Y. Abarbanel, I. Beer, L. Glushovsky, S. Keidar, and Y. Wolfsthal, "Focs: Automatic generation of simulation checkers from formal specifications," in CAV '00: Proceedings of the 12th International Conference on Computer Aided Verification. London, UK: Springer-Verlag, 2000, pp. 538-542.
-
(2000)
CAV '00: Proceedings of the 12th International Conference on Computer Aided Verification
, pp. 538-542
-
-
Abarbanel, Y.1
Beer, I.2
Glushovsky, L.3
Keidar, S.4
Wolfsthal, Y.5
-
14
-
-
33751406386
-
An assertion library for on-chip white-box verification at run-time
-
Natal, RN, Brazil, February
-
J. A. Nacif, F. M. de Paula, H. Foster, C. J. N. Coelho Jr., F. C. Sica, D. C. da Silva Jr., and A. O. Fernandes, "An assertion library for on-chip white-box verification at run-time," in Proceedings of the 4th IEEE Latin-American Test Workshop (LATW'03), Natal, RN, Brazil, February 2003.
-
(2003)
Proceedings of the 4th IEEE Latin-American Test Workshop (LATW'03)
-
-
Nacif, J.A.1
De Paula, F.M.2
Foster, H.3
Coelho Jr., C.J.N.4
Sica, F.C.5
Da Silva Jr., D.C.6
Fernandes, A.O.7
|