Synchro-tokens: Eliminating nondeterminism to enable chip-level test of globally-asynchronous locally-synchronous SoC's

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn 1, Issue , 2004, Pages 410-415

  Heath, Matthew W ^a   Burleson, Wayne P ^a   Harris, Ian G ^b  

^a UNIVERSITY OF MASSACHUSETTS   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONTROL LOGIC; GLOBALLY ASYNCHRONOUS LOCALLY SYNCHRONOUS (GALS); SYNCHRONOUS BLOCK (SB); SYSTEM-ON-A-CHIP (SOC); FUNCTIONAL TEST; GALS ARCHITECTURE; GLOBALLY ASYNCHRONOUS LOCALLY SYNCHRONOUS; INTER-CORE COMMUNICATIONS; NON-DETERMINISM; PERFORMANCE IMPACT; SYSTEM-ON-A-CHIP; TEST METHODOLOGY;

COMPUTER SIMULATION; COMPUTER SYSTEM RECOVERY; DATA ACQUISITION; ERROR ANALYSIS; LOGIC CIRCUITS; OPTIMIZATION; SENSITIVITY ANALYSIS; SIGNAL PROCESSING; SYNCHRONIZATION; APPLICATION SPECIFIC INTEGRATED CIRCUITS; CLOCKS; DESIGN; EXHIBITIONS; PROGRAMMABLE LOGIC CONTROLLERS; SYNCHROS; TESTING;

CMOS INTEGRATED CIRCUITS; ASYNCHRONOUS SEQUENTIAL LOGIC;

EID: 3042604800     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1268881     Document Type: Conference Paper

References (17)

1. Y. Zorian, E. Marinissen, and S. Dey. "Testing Embedded-Core Based System Chips". Proceedings of the 1998 International Test Conference, pp 130-143.
2. F. Gurkaynak, T. Villiger, S. Oetiker, N. Felber, H. Kaeslin, and W. Fichtner. "A Functional Test Methodology for Globally-Asynchronous Locally-Synchronous Systems". ASYNC 2002.
3. D. Josephson, S. Poehlman, and V. Govan. "Debug Methodology for the McKinley Processor". Proceedings of the 2001 International Test Conference, pp 451-460.
4. J. Katz and R. Rajsuman. "A New Paradigm in Test for the Next Millennium". Proceedings of the 2000 International Test Conference, pp 468-476.
5. F. Rosenberger, C. Molnar, T. Chaney, and T.-P. Fang. "Q-Modules: Internally-Clocked Delay Insensitive Modules". IEEE Transactions on Computers, Vol. 37, No. 9, September 1988, pp. 1005-1018.
6. W. S. VanScheik and R. F. Tinder. "High Speed Externally Asynchronous / Internally Clocked Systems". IEEE Trans. on Computers, July 1997, pp. 824-829.
7. S. Kim and R. Sridhar. "Hierarchical Synchroization Scheme Using Self-Timed Mesochronous Interconnections". 1997 IEEE ISCAS, pp. 1824-1827.
8. W. Lim. "Design Methodology for Stoppable Clock Systems". IEE Proceedings, Vol. 133, Part E, No. 1, January 1986, pp 65-69.
9. K. Yun and A. Dooply. "Pausible Clocking-Based Heterogeneous Systems". IEEE Transactions on VLSI Systems, Vol. 7, No. 4, December 1999, pp. 482-488.
10. J. Muttersbach, T. Villiger, and W. Fichtner. "Practical Design of Globally-Asynchronous Locally-Synchronous Systems". ASYNC 2000, pp. 52-59.
11. D. Chapiro. "Globally-Asynchronous Locally-Synchronous Systems". PhD Thesis, Stanford University, Report No. STAN-CS-84-1026, Oct. 1984.
12. P. Nilsson and M. Torkelson. "A Monolithic Digital Clock-Generator for On-Chip Clocking of Custom DSP's". IEEE JSSC, May 1996, pp. 700-706.
13. M. Greenstreet. "Implementing a STARI Chip". Proceedings of the 1995 IEEE ICCD, pp. 38-43.
14. D. Bhavsar, D. Akeson, M. Gowan, and D. Jackson. "Testability Access of the High Speed Test Features in the Alpha 21264 Microprocessor". Proceedings of the 1998 International Test Conference, pp. 487-495.
15. J. Sulistyo and D. Ha. "Developing Standard Cells for TSMC 0.25um Technology under MOSIS DEEP Rules". Department of ECE, Virginia Tech, Technical Report VISC-2002-02, April 2002.
16. V. Iyengar, K. Chakrabarty, and E. J. Marinissen. "Test Wrapper and Test Access Mechanism CoOptimization for System-on-a-Chip". JETTA, Vol. 18, April 2002, pp. 213-230.
17. R. Javagal, A. Datta, and S. Ghosh. "Detecting Deadlocks in Distributed Systems". IEEE ISCAS, Vol. 2, 1991, pp. 1013-1016.