Design for (physical) debug for silicon microsurgery and probing of flip-chip packaged integrated circuits

IEEE International Test Conference (TC)

Volumn , Issue , 1999, Pages 877-882

  Livengood, Richard H ^a   Medeiros, Donna ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DESIGN FOR TESTABILITY; ELECTRONICS PACKAGING; ERROR DETECTION; FLIP CHIP DEVICES; PRODUCT DEVELOPMENT; SILICON;

FLIP CHIP PACKAGED INTEGRATED CIRCUITS; FLIP CHIP PACKAGING; ON-CHIP PROBING; PRODUCT ANALYSIS; SILICON MICROSURGERY;

INTEGRATED CIRCUIT TESTING;

EID: 0033343250     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)