CADRE: Cycle-accurate deterministic replay for hardware debugging

Proceedings of the International Conference on Dependable Systems and Networks

Volumn 2006, Issue , 2006, Pages 301-310

  Sarangi, Smruti R ^a   Greskamp, Brian ^a   Torrellas, Josep ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK CYCLE GRANULARITY; CYCLE ACCURATE DETERMINISTIC REPLAY (CADRE); SYNCHRONOUS BUSES;

COMPUTER ARCHITECTURE; COMPUTER DEBUGGING; COST EFFECTIVENESS; MULTIPROCESSING PROGRAMS; SERVERS;

COMPUTER HARDWARE;

EID: 33845563448     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSN.2006.19     Document Type: Conference Paper

References (22)

1. Intel VTune performance analyzer, http://www.intel.com/vtune.
2. Intel 82801EB I/O Controller Hub 5 (ICH5) and Intel 82801ER I/O Controller Hub 5 R (ICH5R) Datasheet, 2003.
3. Intel E7525 Memory Controller Hub (MCH) Datasheet, 2003.
4. F. Bacchini et al. Verification: What works and what doesn't. In DAC, page 274, 2004.
5. L. Bening and H. Foster. Principles of Verifiable RTL Design. Kluwer Academic Publishers, 2 edition, 2001.
6. B. Bentley. Validating the Intel Pentium 4 microprocessor. In Dependable Systems and Networks, pages 493-500, 2001.
7. P. Dahlgren, P. Dickinson, and I. Parulkar. Latch divergency in microprocessor failure analysis. In ITC, pages 755-763, 2003.
8. W. J. Dally and J. W. Poulton. Digital Systems Engineering. Cambridge University Press, 1998.
9. M. W. Heath, W. P. Burleson, and I. G. Harris. Synchro-tokens: Eliminating nondeterminism to enable chip-level test of globally-asynchronous locally-synchronous SoC's. In DATE, 2004.
10. http://public.itrs.net. International technology roadmap for semiconductors, 2002.
11. HyperTransport Technology Consortium. HyperTransport I/O link specification revision 2.00b, 2005.
12. I.Silas et al. System level validation of the Intel Pentium-M processor. Intel Technology Journal, 7(2), May 2003.
13. D. D. Josephson, S. Poehhnan, and V. Govan. Debug methodology for the McKinley processor. In ITC, pages 451-460, 2001.
14. N. Lynch. Distributed Algorithms. Morgan-Kauffman Publishers, 1996.
15. K. Mohanram and N. A. Touba. Eliminating non-determinism during test of high-speed source synchronous differential buses. In VTS, pages 121-127, 2003.
16. M. Prvulovic, Z. Zhang, and J. Torrellas. ReVive: Cost-effective architectural support for rollback recovery in shared-memory multiprocessors. In ISCA, pages 111-122, 2002.
17. L. Sartori and B. G. West. The path to one-picosecond accuracy. In ITC, pages 619-627, 2000.
18. D. Sorin, M. Martin, M. Hill, and D. Wood. SafetyNet: Improving the availability of shared memory multiprocessors with global checkpoint/recovery. In ISCA, pages 123-134, 2002.
19. Agilent Systems. Agilent technologies E8045B analysis probe system for the Intel Pentium 4 processor in the 775-land package, 2004.
20. J. J. P. Tsai, K. Fang, H. Chen, and Y. Bi. A noninterference monitoring and replay mechanism for real-time software testing and debugging. IEEE Trans. Software Eng., 16(8):897-916, 1990.
21. D. Vahia. Personal communication. Sun Microsystems, June 2005.
22. M. Xu, R. Bodík, and M. D. Hill. A "Flight Data Recorder" for enabling full-system multiprocessor deterministic replay. In ISCA, 2003.