On the cusp of a validation wall

IEEE Design and Test of Computers

Volumn 24, Issue 2, 2007, Pages 193-196

  Patra, Priyadarsan ^a,b  

^a INTEL CORPORATION   (United States)

^b NONE   (United States)

Author keywords

Logic; Low DPM; Modular validation; Validation wall; Virtual platform

Indexed keywords

MODULAR VALIDATION; POSTSILICON VALIDATION; VALIDATION WALL; VIRTUAL PLATFORM;

COMPUTER HARDWARE; COMPUTER SOFTWARE; ELECTRONICS INDUSTRY; MICROPROCESSOR CHIPS; SPECIFICATIONS;

SEMICONDUCTING SILICON;

EID: 34347392507     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2007.54     Document Type: Article

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