Patching processor design errors with programmable hardware

IEEE Micro

Volumn 27, Issue 1, 2007, Pages 12-25

  Sarangi, Smruti ^a   Narayanasamy, Satish ^b   Carneal, Bruce ^b   Tiwari, Abhishek ^a   Calder, Brad ^b,c   Torrellas, Josep ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Design defects in real processors; Hardware errors; Microarchitecture for fault tolerance; Processor errata analysis

Indexed keywords

COMPUTER SYSTEMS PROGRAMMING; ERROR DETECTION; FAULT TOLERANT COMPUTER SYSTEMS; PATTERN MATCHING;

HARDWARE ERRORS; MICROARCHITECTURE; PROCESSOR ERRATA ANALYSIS;

PROGRAM PROCESSORS;

EID: 34249788697     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2007.19     Document Type: Article

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